Complementary MOS circuit having decreased parasitic capacitance

Claim 1

A complementary MOS circuit comprising: a complementary MOS circuit means comprising an n-channel MOS transistor on a semiconductor substrate of p-type and a p-channel MOS transistor on a semiconductor substrate n-type, the gate terminals of said n-channel MOS transistor and said p-channel MOS transistor being connected electrically in common to an input terminal, and the drain terminals of said n-channel MOS transistor and said p-channel MOS transistor being connected electrically in common to an output terminal; first power supply means for applying first and second externally supplied voltages to the substrate terminals, respectively, of said n-channel MOS transistor and said p-channel MOS transistor; second power supply means for applying first and second internally supplied voltages to the source terminals, respectively, of said n-channel MOS transistor and said p-channel MOS transistor; and a constant voltage circuit means comprising a means for receiving through one of a first and a second externally supplied power terminal, one of a first and a second externally supplied voltage and for converting said one externally supplied voltage into one of said first and second internally supplied voltages; said first and second externally supplied power supply terminals being electrically connected to the substrate terminals, respectively, of said n-channel MOS transistor and said p-channel MOS transistor; said first and second internally supplied voltages being connected electrically to the source terminals, respectively, of said n-channel MOS transistor and said p-channel MOS transistor; and wherein the absolute value of the difference between said first and second internally supplied voltages is maintained constant regardless of the variation in the absolute value of the difference between said first and second externally supplied voltages.