Patent US5089738A successfully refreshed from Google Patents.
EP0063483A2
Expired / Lapsed
EP
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Semiconductor integrated circuit
Assignee: Hitachi Ltd
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Filing: 1982-04-16
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Granted: —
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Expires: 2002-04-16
Abstract
Abstract A semiconductor memory has a circuit (40) including a memory array (MA) and direct peripheral circuits (SA, PC, XD, YD); and an indirect peripheral circuit (50, 50A). The transistors of the circuit (40) are made smaller than those of the circuit (50, 50A) in order to increase the density of integration, and are fed from a generator (30) with a lower supply voltage (V DP ) than the chip supply voltage (V cc ) since their breakdown voltages are also lower. The circuit (50, 50A) receives external signals varying in the range of the higher supply voltage (V cc ) and supplies signals to the circuit (40) which vary in the range of the lower supply voltage (V DP ).
Inventors
- 👤 Kiyoo Itoh
- 👤 Ryoichi Hori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 20:45
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C5/00; G11C5/14; G11C5/145; G11C5/147
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
133 words
A semiconductor integrated circuit comprising: a first circuit (30) arranged to receive a first power source voltage (V ) and to generate a predetermined second power source voltage (V DP ) which is lower than said first power source voltage; a second circuit (50,50A) arranged to receive said first power source voltage (V ) and to generate a second pulse signal for use with said second power source voltage, in response to a first pulse signal which varies within the same voltage range as that of said first power source voltage; and a third circuit (40) arranged to receive said second power source voltage and responsive to said second pulse signal, said third circuit including circuit elements (Q ) having a smaller size than that of the circuit elements forming said first circuit.
Claim 2
Dependent Claim
133 words
A semiconductor integrated circuit comprising: a first circuit (30) arranged to receive a first power source voltage (V ) and to generate a predetermined second power source voltage (V DP ) which is lower than said first power source voltage; a second circuit (50,50A) arranged to receive said first power source voltage (V ) and to generate a second pulse signal for use with said second power source voltage, in response to a first pulse signal which varies within the same voltage range as that of said first power source voltage; and a third circuit (40) arranged to receive said second power source voltage and responsive to said second pulse signal, said third circuit including circuit elements (Q ) having a smaller size than that of the circuit elements forming said first circuit.
Claim 3
Dependent Claim
42 words
A semiconductor integrated circuit according to claim 1, wherein said first power source voltage (V cc ) and said first pulse signal are the power source voltage and the pulse signal, respectively, which are fed from the outside of said integrated circuit.
Claim 4
Dependent Claim
51 words
A semiconductor integrated circuit according to claim 1 or 2, wherein said first circuit (30) is made operative to hold said second power source voltage (V DP ) at a predetermined level even if said first power source voltage (V cc ) varies to a higher level than said predetermined level.
Claim 5
Dependent Claim
45 words
A semiconductor integrated circuit according to claim 3, wherein said second circuit (50,50A) is made operative to hold the higher level of said second pulse signal at a predetermined level even if the higher level of said first pulse signal varies above a predetermined level.
Claim 6
Dependent Claim
35 words
A semiconductor integrated circuit according to any one of the preceding claims, wherein the area occupied by said third circuit (40) is larger than that occupied in said integrated circuit by said second circuit (50,50A).
Claim 7
Dependent Claim
29 words
A semiconductor integrated circuit according to any one of the preceding claims wherein said third circuit (40) includes a plurality of identical circuit elements (MC) which are regularly arranged.
Claim 8
Dependent Claim
73 words
A semiconductor integrated circuit according to claim 6, wherein said third circuit includes pluralities of word lines (W), data lines (D, D) and memory cells (MC), which are regularly arranged, respectively; and wherein said second circuit (50,50A) is made operative to control the operation of said third circuit in response to an address signal (A. - A j , A. ' - A. ') which is received thereby as said first pulse signal.
Claim 9
Dependent Claim
146 words
A semiconductor integrated circuit according to claim 7, wherein said second circuit includes: a circuit (50) arranged to respond to said address signal received for generating an internal address signal (a. - a., a i ' - a.'), which varies within the same voltage range as that of said second power source voltage (V o p), as one of said second pulse signals; and a circuit (50A) for generating pulses for driving said word lines as another of said second pulse signals, and wherein said third circuit includes: a circuit (XD) for feeding said word line drive pulses to the word line (W) which is designated by said internal address signal; a data line (I/O, I/O ) shared among said plural data lines (D,5); and a circuit (YD) for connecting the data line, which is designated by said internal address signal, with said common data line.
Claim 10
Dependent Claim
70 words
A semiconductor integrated circuit according to claim 8, wherein said word line drive pulse generating circuit (50A) is a circuit for generating a plurality of word line drive pulses, and wherein said word line drive pulse feeding circuit is arranged to respond to said plural word line drive pulses for boosting the voltage of said designated word line to a voltage which is higher than said second power source voltage.
Claim 11
Dependent Claim
86 words
A semiconductor integrated circuit according to claim 8 or 9, wherein said second circuit (50) further includes means for generating pre-charge pulses (φ o ) which have a higher voltage than said second power source voltage (V DP ) for pre-charging a predetermined portion of said third circuit which includes said data lines (D,D), and wherein said third circuit includes a circuit (PC) arranged to receive said second power source voltage and said pre-charge pulses for pre-charging said predetermined portion to said second power source voltage.
Claim 12
Dependent Claim
74 words
A semiconductor integrated circuit according to any one of the preceding claims, wherein said first and second circuits include a plurality of insulated gate type field effect transistors, and wherein said third circuit includes a plurality of insulated gate type field effect transistors (Q ) having smaller gate oxide film thickness (t ox ), channel length (L) and threshold voltage (V th ) than those of the transistors of said first and second circuits.
Claim 13
Dependent Claim
38 words
A semiconductor integrated circuit according to any one of the preceding claims, wherein said third circuit (40) has a smaller element separation width (L ) than that of the circuit elements which construct said first and second circuits.
Claim 14
Dependent Claim
70 words
A semiconductor integrated circuit according to any one of the preceding claims, wherein the thickness (t ) of the insulating film, which is positioned on a semiconductor substrate between adjacent insulated gate type field effect transsistors of said third circuit, is made smaller than that of the insulating film which is positioned on said semiconductor substrate between adjacent insulated gate type field effect transistors of said first and second circuits.
Claim 15
Dependent Claim
35 words
A semiconductor integrated circuit according to claim 1, wherein the depth (x.) of the diffusion layer in said third circuit is made smaller than those of the diffusion layers in said first and second circuits.
References Cited (Backward Citations)
No citation records indexed.
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