US4585955A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Internally regulated power voltage circuit for MIS semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1983-11-30
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Granted: 1986-04-29
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Expires: 2003-11-30
Abstract
Abstract A MIS semiconductor integrated circuit is one which contains an internal circuit. In the internal circuit, an externally supplied power source voltage supplied to a power source voltage terminal is supplied to the voltage input terminal of a voltage dropping circuit. The voltage at a voltage output terminal of the voltage dropping circuit is detected by a voltage detecting circuit containing an inverting circuit with a predetermined threshold voltage. The voltage dropping circuit is switch-controlled by applying the detected voltage to the control terminal thereof. The voltage output terminal of the voltage dropping circuit provides an internal power source voltage which is formed by dropping the externally supplied power source voltage. An internal circuit containing MOSFETs with an effective channel length of 1 μm or less is driven by the internal power source voltage.
Inventors
- 👤 Yukimasa Uchida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:00
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; H; H10; H10D; H10D89/00; H10D89/211; H10D89/213
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
229 words
An MIS semiconductor integrated circuit comprising: (a) a power source voltage terminal externally supplied with a power voltage; (b) voltage dropping means, having a control terminal, a voltage input terminal connected to said power source voltage terminal to receive said power voltage and a voltage output terminal, for controllably dropping said power voltage and supplying said dropped power voltage to said voltage output terminal as a function of an input control signal supplied to said control terminal; (c) voltage detection means, including a MISFET having a gate, for comparing said dropped power voltage at said voltage output terminal of said voltage dropping means to a prescribed threshold voltage level by inputting said dropped power voltage to said gate of said MISFET and for supplying a signal corresponding to the result of said comparison to said control terminal of said voltage dropping means as said input control signal; and (d) an internal circuit including a CMOS inverter having a p channel and an n channel MISFET, with channel regions of said p channel and n channel MISFETs connected in series, said p channel and n channel MISFETs having a common gate and with an output obtained from a common node of said MISFETs and with said dropped power voltage from said voltage output terminal of said voltage dropping means being supplied to one end of said series connected channel regions.
Claim 2
Dependent Claim
229 words
An MIS semiconductor integrated circuit comprising: (a) a power source voltage terminal externally supplied with a power voltage; (b) voltage dropping means, having a control terminal, a voltage input terminal connected to said power source voltage terminal to receive said power voltage and a voltage output terminal, for controllably dropping said power voltage and supplying said dropped power voltage to said voltage output terminal as a function of an input control signal supplied to said control terminal; (c) voltage detection means, including a MISFET having a gate, for comparing said dropped power voltage at said voltage output terminal of said voltage dropping means to a prescribed threshold voltage level by inputting said dropped power voltage to said gate of said MISFET and for supplying a signal corresponding to the result of said comparison to said control terminal of said voltage dropping means as said input control signal; and (d) an internal circuit including a CMOS inverter having a p channel and an n channel MISFET, with channel regions of said p channel and n channel MISFETs connected in series, said p channel and n channel MISFETs having a common gate and with an output obtained from a common node of said MISFETs and with said dropped power voltage from said voltage output terminal of said voltage dropping means being supplied to one end of said series connected channel regions.
Claim 3
Dependent Claim
78 words
An MIS semiconductor integrated circuit according to claim 1, wherein said voltage detection means includes a CMOS inverter having a second p channel and a second n channel MISFET, with the channel regions of said second p channel and second n channel MISFETs connected in series and with said second p channel and n second channel MISFETs having a common gate to which said dropped voltage from said voltage output terminal of said voltage dropping means is supplied.
Claim 4
Dependent Claim
47 words
An MIS semiconductor integrated circuit according to claim 1, wherein said voltage detection means includes an inverter comprising one MISFET and a load resistance, said one MISFET having a gate to which said dropped voltage at said voltage output terminal of said voltage dropping means is supplied.
Claim 5
Dependent Claim
76 words
An MIS semiconductor integrated circuit according to claim 1, wherein said voltage detection means includes a source of constant voltage and a differential amplifier having a pair of input MISFETs which each have a gate, with said dropped voltage from said voltage output terminal of said voltage dropping means being supplied to one of said gates of said input MISFETs and said constant voltage being supplied to the other of said gates of said input MISFETs.
Claim 6
Dependent Claim
19 words
A MIS semiconductor integrated circuit according to claim 4, in which said voltage dropping means is a switching element.
Claim 7
Dependent Claim
17 words
A MIS semiconductor integrated circuit according to claim 5, in which said switching element is a MISFET.
Claim 8
Dependent Claim
18 words
A MIS semiconductor integrated circuit according to claim 5, in which said switching element is a bipolar transistor.
Claim 9
Dependent Claim
67 words
An MIS semiconductor integrated circuit according to claim 4, wherein said voltage detection means includes a CMOS inverter having a second pair of MISFETs, one being n channel and one being p channel, with the channel regions of said second pair of MISFETs connected in series, and with said second pair of MISFETs having a common gate to which the output of said differential amplifier is supplied.
Claim 10
Dependent Claim
40 words
An MIS semiconductor integrate circuit according to claim 4, wherein said voltage detection means includes an inverter comprising one MISFET and a load resistance, said one MISFET having a gate to which the output of said differential amplifier is supplied.
Claim 11
Dependent Claim
22 words
A MIS semiconductor integrated circuit according to claim 4, in which said source of constant voltage comprises a plurality of series-connected diodes.
Claim 12
Dependent Claim
20 words
A MIS semiconductor integrated circuit according to claim 10, in which programmable fuses are connected in parallel to said diodes.
Claim 13
Dependent Claim
28 words
A MIS semiconductor integrated circuit according to claim 4, in which the effective channel length of said MISFETs contained in said internal circuit is 1 μm or less.
Claim 14
Dependent Claim
19 words
A MIS semiconductor integrated circuit according to claim 1, in which said voltage dropping means is a switching element.
Claim 15
Dependent Claim
17 words
A MIS semiconductor integrated circuit according to claim 13, in which said switching element is a MISFET.
Claim 16
Dependent Claim
18 words
A MIS semiconductor integrated circuit according to claim 13, in which said switching element is a biopolar transistor.
Claim 17
Dependent Claim
28 words
A MIS semiconductor integrated circuit according to claim 1, in which the effective channel length of said MISFETs contained in said internal circuit is 1 μm or less.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |