US4472647A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for interfacing with both TTL and CMOS voltage levels
Assignee: Motorola Solutions Inc
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Filing: 1982-08-20
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Granted: 1984-09-18
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Expires: 2002-08-20
Abstract
Abstract A voltage compatible circuit for providing TTL and CMOS level inputs and/or outputs is provided. An input signal level detection portion generates either a CMOS or a TTL mode signal in response to a voltage level selection signal. One or more input buffers and/or output buffers is coupled to the CMOS and TTL mode signals. The input buffers are responsive to input signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. The output buffers provide output signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. A reference voltage portion and a bias generator portion are coupled to the input and output buffers to provide the predetermined voltage levels.
Inventors
- 👤 Robert N. Allgood
- 👤 Stephen H. Kelley
- 👤 Richard W. Ulmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585; H03K19/017509; H03K19/017518; H03K19/018507; H03K19/018521; H03K19/01855; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
246 words
A circuit which may receive an input signal within a predetermined CMOS voltage levels in response to a voltage level selection signal having at least a predetermined value, and which otherwise may receive an input signal within predetermined TTL voltage level inputs, comprising: input signal level detection means characterized by receiving said voltage level selection signal, and providing a CMOS mode control signal at a first output when said selection signal is equal to or greater than said predetermined value, and otherwise providing a TTL mode control signal at a second output; reference voltage means characterized by receiving said selection signal at a first input and having a second input coupled to the first output of said input signal level detection means, for providing at an output a reference voltage which is referenced to the voltage of said selection signal; and input buffer means having a first input coupled to the first output of said input signal level detection means, a second input coupled to the second output of said input signal level detection means, and a third input coupled to the output of said reference voltage means, for receiving a CMOS voltage level input signal in response to said CMOS mode control signal, and for receiving a TTL voltage level input signal in response to said TTL mode control signal, said input buffer means having an output for providing an input buffer output signal within predetermined CMOS voltage levels in response to the input signal.
Claim 2
Dependent Claim
246 words
A circuit which may receive an input signal within a predetermined CMOS voltage levels in response to a voltage level selection signal having at least a predetermined value, and which otherwise may receive an input signal within predetermined TTL voltage level inputs, comprising: input signal level detection means characterized by receiving said voltage level selection signal, and providing a CMOS mode control signal at a first output when said selection signal is equal to or greater than said predetermined value, and otherwise providing a TTL mode control signal at a second output; reference voltage means characterized by receiving said selection signal at a first input and having a second input coupled to the first output of said input signal level detection means, for providing at an output a reference voltage which is referenced to the voltage of said selection signal; and input buffer means having a first input coupled to the first output of said input signal level detection means, a second input coupled to the second output of said input signal level detection means, and a third input coupled to the output of said reference voltage means, for receiving a CMOS voltage level input signal in response to said CMOS mode control signal, and for receiving a TTL voltage level input signal in response to said TTL mode control signal, said input buffer means having an output for providing an input buffer output signal within predetermined CMOS voltage levels in response to the input signal.
Claim 3
Dependent Claim
115 words
The circuit of claim 1 wherein said reference voltage means provides a second reference voltage referenced to the voltage of the selection signal at a second output, and further comprising: output buffer means having first and second inputs coupled to the first and second outputs of said input signal level detection means, respectively, a third input for receiving a data signal, and a fourth input coupled to the second output of the reference voltage means, for providing a circuit output signal in response to the data signal, said output signal having CMOS voltage levels in response to said CMOS mode control signal, and having TTL voltage levels in response to said TTL mode control signal.
Claim 4
Dependent Claim
129 words
The circuit of claims 1 or 2 wherein said input buffer means further comprise: a plurality of input buffers, each of which has first and second inputs coupled to the first and second outputs of the input signal level detection means, a third input coupled to the first output of said reference voltage means, and a fourth input which is coupled to a predetermined one of a plurality of input signals, each input buffer providing an input buffer output signal having CMOS voltage levels, each input buffer being able to receive an input signal having CMOS voltage levels in response to said CMOS mode control signal, and each input buffer being able to receive an input signal having TTL voltage levels in response to said TTL mode control signal.
Claim 5
Dependent Claim
229 words
A circuit for providing an output signal within predetermined CMOS voltage levels in response to a voltage level selection signal having at least a predetermined value and within predetermined TTL voltage level inputs otherwise, comprising: input signal level detection means characterized by receiving said voltage level selection signal, and providing a CMOS mode control signal at a first output when said selection signal is equal to or greater than said predetermined value, and otherwise providing a TTL mode control signal at a second output; reference voltage means characterized by receiving said selection signal at a first input and having a second input coupled to the first output of said input signal level detection means, for providing a reference voltage which is referenced to the voltage of said selection signal at an output; and output buffer means having a first input coupled to the first output of said input signal level detection means, a second input coupled to the second output of said input signal level detection means, a third input coupled to the output of said reference voltage means, and a fourth input for receiving an input data signal, for providing an output signal having a logic level related to the input data signal, and having CMOS voltage levels in response to said CMOS mode control signal or TTL voltage levels in response to said TTL mode control signal.
Claim 6
Dependent Claim
229 words
A circuit for providing an output signal within predetermined CMOS voltage levels in response to a voltage level selection signal having at least a predetermined value and within predetermined TTL voltage level inputs otherwise, comprising: input signal level detection means characterized by receiving said voltage level selection signal, and providing a CMOS mode control signal at a first output when said selection signal is equal to or greater than said predetermined value, and otherwise providing a TTL mode control signal at a second output; reference voltage means characterized by receiving said selection signal at a first input and having a second input coupled to the first output of said input signal level detection means, for providing a reference voltage which is referenced to the voltage of said selection signal at an output; and output buffer means having a first input coupled to the first output of said input signal level detection means, a second input coupled to the second output of said input signal level detection means, a third input coupled to the output of said reference voltage means, and a fourth input for receiving an input data signal, for providing an output signal having a logic level related to the input data signal, and having CMOS voltage levels in response to said CMOS mode control signal or TTL voltage levels in response to said TTL mode control signal.
Claim 7
Dependent Claim
132 words
The circuit of claim 4 wherein said reference voltage means provides a second reference voltage referenced to the voltage of the selection signal at a second output, and further comprising: Input buffer means having first and second inputs coupled to the first and second outputs of said input signal level detection means, respectively, and a third input coupled to the second output of said reference voltage means at a second output thereof, for accepting an input signal having a CMOS voltage level in response to said CMOS mode control signal, and for accepting a TTL voltage level input signal in response to said TTL mode control signal, and an output for providing, in response to the input signal, an input buffer output signal having voltage levels within a predetermined CMOS voltage range.
Claim 8
Dependent Claim
17 words
The circuit of claim 5 wherein said input buffer means further comprise a plurality of input buffers.
Claim 9
Dependent Claim
19 words
The circuit of claim 5 or 6 wherein said output buffer means further comprise a plurality of output buffers.
Claim 10
Dependent Claim
193 words
A circuit for receiving a CMOS input signal in response to a select signal being within a first predetermined range, and for receiving a TTL input signal in response to the select signal being within a second predetermined range, wherein the first and second predetermined ranges are adjacent one another, comprising: input signal level detection means characterized by receiving said select signal, for detecting whether said select signal is in said first or said second predetermined range; reference voltage means coupled to said input signal level detection means and characterized by receiving said select signal, for providing a reference voltage which is referenced to said select signal; and input buffer means coupled to said input detection means and to said reference voltage means, for receiving an input signal having a CMOS voltage level in response to said select signal being within said first predetermined range, and for receiving an input signal having a CMOS voltage level in response to said select signal being within said adjacent second predetermined range, said input buffer means providing an output signal, in response to the input signal, having a logic level within a predetermined CMOS voltage range.
Claim 11
Dependent Claim
193 words
A circuit for receiving a CMOS input signal in response to a select signal being within a first predetermined range, and for receiving a TTL input signal in response to the select signal being within a second predetermined range, wherein the first and second predetermined ranges are adjacent one another, comprising: input signal level detection means characterized by receiving said select signal, for detecting whether said select signal is in said first or said second predetermined range; reference voltage means coupled to said input signal level detection means and characterized by receiving said select signal, for providing a reference voltage which is referenced to said select signal; and input buffer means coupled to said input detection means and to said reference voltage means, for receiving an input signal having a CMOS voltage level in response to said select signal being within said first predetermined range, and for receiving an input signal having a CMOS voltage level in response to said select signal being within said adjacent second predetermined range, said input buffer means providing an output signal, in response to the input signal, having a logic level within a predetermined CMOS voltage range.
Claim 12
Dependent Claim
181 words
A circuit for providing a CMOS output signal in response to a select signal being within a first predetermined range, and for providing a TTL output signal in response to said select signal being within a second predeteremined range, wherein the first and second predetermined ranges are adjacent one another, comprising: input signal level detection means characterized by receiving said select signal, for detecting whether said select signal is in said first or said second predetermined range; reference voltage means coupled to said input signal level detection means and adapted to receive said select signal, for providing a reference voltage which is referenced to said select signal; and output buffer means coupled to said input signal level detection means and to said reference voltage means, for receiving an input data signal and providing a circuit output signal having a logic level related to the input data signal and having CMOS voltage levels in response to said select signal being within said first predetermined range, and TTL voltage levels in response to said select signal being within said adjacent second predetermined range.
Claim 13
Dependent Claim
181 words
A circuit for providing a CMOS output signal in response to a select signal being within a first predetermined range, and for providing a TTL output signal in response to said select signal being within a second predeteremined range, wherein the first and second predetermined ranges are adjacent one another, comprising: input signal level detection means characterized by receiving said select signal, for detecting whether said select signal is in said first or said second predetermined range; reference voltage means coupled to said input signal level detection means and adapted to receive said select signal, for providing a reference voltage which is referenced to said select signal; and output buffer means coupled to said input signal level detection means and to said reference voltage means, for receiving an input data signal and providing a circuit output signal having a logic level related to the input data signal and having CMOS voltage levels in response to said select signal being within said first predetermined range, and TTL voltage levels in response to said select signal being within said adjacent second predetermined range.
References Cited (Backward Citations)
US4032795A
Cited
US4242604A
Cited
US4287439A
Cited
US4342926A
Cited
US4380710A
Cited
US4392067A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-18 | 1988-03-19 | 1988-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-18 | 1992-03-19 | 1992-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-18 | 1996-03-19 | 1996-09-18 | $7700.00 | Window Closed / Lapsed |