US4032795A
Expired / Lapsed
US
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Input buffer
Assignee: Solitron Devices Inc
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Filing: 1976-04-14
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Granted: 1977-06-28
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Expires: 1996-04-14
Abstract
Abstract A circuit of complementary field effect devices whose logical input threshold voltage can be varied between levels suitable for TTL logic or CMOS or PMOS or other logic under control of an electrical signal in real time.
Inventors
- 👤 Robert R. Hale
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K19/018585
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
138 words
A signal processing circuit controlling output voltage comprising: a series of field effect transistors including first and second such transistors of one conductivity type connected to a third such transistor of differing conductivity across a power source; a fourth field effect transistor connected between said third such transistor and the power source in parallel with said first and second such transistors; means to provide a control signal to said first field effect transistor and an inverted signal thereof to said fourth field effect transistor; means to provide a data signal to said third of such transistors and to the second field effect transistor; and means to provide an output of said circuit from the connection of said first and second such transistors to the power source from said fourth field effect transistor to said third field effect transistor.
Claim 2
Dependent Claim
138 words
A signal processing circuit controlling output voltage comprising: a series of field effect transistors including first and second such transistors of one conductivity type connected to a third such transistor of differing conductivity across a power source; a fourth field effect transistor connected between said third such transistor and the power source in parallel with said first and second such transistors; means to provide a control signal to said first field effect transistor and an inverted signal thereof to said fourth field effect transistor; means to provide a data signal to said third of such transistors and to the second field effect transistor; and means to provide an output of said circuit from the connection of said first and second such transistors to the power source from said fourth field effect transistor to said third field effect transistor.
Claim 3
Dependent Claim
33 words
The circuit of claim 1 and further comprising in said means to provide a data signal a protective circuit to prevent overloading of said third such transistor and the second field effect transistor.
Claim 4
Dependent Claim
132 words
An input buffer circuit comprising: a control signal circuit having a first field effect transistor receiving a control signal at its gate for controlling supply voltage therethrough and at least one second field effect transistor having its gate connected via an inverter to the aforesaid control signal for controlling supply voltage therethrough so as to be selectively operable by high and low control signals; data signal circuit having at least one third field effect transistor of a conductivity type the same as the first in the path of supply voltage from said first field effect transistor and at least one fourth field effect transistor in the path of supply voltage from said third and said second; and at least one output means in the path of said fourth field effect transistor means.
Claim 5
Dependent Claim
132 words
An input buffer circuit comprising: a control signal circuit having a first field effect transistor receiving a control signal at its gate for controlling supply voltage therethrough and at least one second field effect transistor having its gate connected via an inverter to the aforesaid control signal for controlling supply voltage therethrough so as to be selectively operable by high and low control signals; data signal circuit having at least one third field effect transistor of a conductivity type the same as the first in the path of supply voltage from said first field effect transistor and at least one fourth field effect transistor in the path of supply voltage from said third and said second; and at least one output means in the path of said fourth field effect transistor means.
Claim 6
Dependent Claim
39 words
The circuit of claim 3 and further comprising multiple data signal circuits having a multiplicity of said third and fourth field effect transistors as well as a multiple of said second field effect transistors in said control signal circuit.
Claim 7
Dependent Claim
75 words
The input buffer circuit of claim 4 and further characterized by a means to connect said control signal circuit to said first field effect transistor and the complement thereof to each of the multiple of said second field effect transistors and a plurality of data signal circuit means for each one of the multiple of said third and fourth field effect transistors with a plurality of output means for selective data transfer by common control.
Claim 8
Dependent Claim
138 words
A circuit comprising: a first series circuit of field effect devices including first and second P type field effect transistors concluding with a third N type field effect transistor; a fourth P type field effect transistor connected to said third field effect transistor so as to be in parallel with the first and second field effect transistors connection with said third field effect transistor; means to provide a control signal to said first field effect transistor, said means also providing a complementary control signal to said fourth field effect transistor; data input means to control the gating of said second field effect transistor and said third field effect transistor; and means to derive output signals at the connection of the first and second field effect transistors and the fourth field effect transistor to the third field effect transistor.
Claim 9
Dependent Claim
138 words
A circuit comprising: a first series circuit of field effect devices including first and second P type field effect transistors concluding with a third N type field effect transistor; a fourth P type field effect transistor connected to said third field effect transistor so as to be in parallel with the first and second field effect transistors connection with said third field effect transistor; means to provide a control signal to said first field effect transistor, said means also providing a complementary control signal to said fourth field effect transistor; data input means to control the gating of said second field effect transistor and said third field effect transistor; and means to derive output signals at the connection of the first and second field effect transistors and the fourth field effect transistor to the third field effect transistor.
Claim 10
Dependent Claim
17 words
The circuit of claim 6 and further comprising an overload protective circuit for the data input means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-27 | 1980-12-27 | 1981-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-27 | 1984-12-27 | 1985-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-27 | 1988-12-27 | 1989-06-28 | $7700.00 | Window Closed / Lapsed |