US4475050A
Expired / Lapsed
US
⏱️ 0.0 years remaining
TTL To CMOS input buffer
Assignee: Motorola Solutions Inc
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Filing: 1983-05-05
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Granted: 1984-10-02
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Expires: 2003-05-05
Abstract
Abstract A CMOS level shifter with a reference voltage generator provides a TTL to CMOS input buffer. The reference voltage generator provides a reference voltage which is responsive to the voltage level of the TTL input signal. The reference voltage is kept sufficiently low to prevent an input P channel transistor from turning on when the TTL input signal is at a logic high even when the voltage level is at a minimum for a logic high.
Inventors
- 👤 Glenn E. Noufer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
324 words
In a TTL to CMOS input buffer, an input circuit for providing an output signal in a first logic state when a TTL input signal is between a TTL supply voltage and a TTL reference voltage, comprising: a first transistor of a first conductivity type having a characteristic threshold voltage and having a control electrode for receiving the TTL signal, a first current electrode coupled to a reference terminal for receiving a CMOS reference voltage, and a second current electrode for providing a first output; a first transistor of a second conductivity type having a control electrode coupled to the control electrode of the first transistor of the first conductivity type, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor of the first conductivity type; a second transistor of the second conductivity type having a first current electrode coupled to a second power supply terminal, a second current electrode for providing the CMOS reference voltage, and a control electrode coupled to a reference terminal; load means coupled between the second power supply terminal and the reference terminal for providing resistance therebetween; a third transistor of the second conductivity type having a first current electrode and a control electrode coupled to the reference terminal, and a second current electrode; a second transistor of the first conductivity type having a first current electrode coupled to the second current electrode of the third transistor of the second conductivity type, a control electrode for receiving the TTL input signal, and a second current electrode; and switch means coupled between the second current electrode of the second transistor of the first conductivity type and the first power supply terminal for providing a low resistance current path therebetween when the TTL signal is at a logic high and for blocking current flow therebetween when the TTL input signal is at a logic low.
Claim 2
Dependent Claim
324 words
In a TTL to CMOS input buffer, an input circuit for providing an output signal in a first logic state when a TTL input signal is between a TTL supply voltage and a TTL reference voltage, comprising: a first transistor of a first conductivity type having a characteristic threshold voltage and having a control electrode for receiving the TTL signal, a first current electrode coupled to a reference terminal for receiving a CMOS reference voltage, and a second current electrode for providing a first output; a first transistor of a second conductivity type having a control electrode coupled to the control electrode of the first transistor of the first conductivity type, a first current electrode coupled to a first power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor of the first conductivity type; a second transistor of the second conductivity type having a first current electrode coupled to a second power supply terminal, a second current electrode for providing the CMOS reference voltage, and a control electrode coupled to a reference terminal; load means coupled between the second power supply terminal and the reference terminal for providing resistance therebetween; a third transistor of the second conductivity type having a first current electrode and a control electrode coupled to the reference terminal, and a second current electrode; a second transistor of the first conductivity type having a first current electrode coupled to the second current electrode of the third transistor of the second conductivity type, a control electrode for receiving the TTL input signal, and a second current electrode; and switch means coupled between the second current electrode of the second transistor of the first conductivity type and the first power supply terminal for providing a low resistance current path therebetween when the TTL signal is at a logic high and for blocking current flow therebetween when the TTL input signal is at a logic low.
Claim 3
Dependent Claim
98 words
The input circuit of claim 1, wherein the switch means comprises: a fourth transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the second transistor of the first conductivity type, a control electrode for receiving the TTL input signal, and a second current electrode; and a fifth transistor of the second conductivity type having a first current electrode and a control electrode coupled to the second current electrode of the fourth transistor of the second conductivity type, and a second current electrode coupled to the first power supply terminal.
Claim 4
Dependent Claim
168 words
A reference voltage generator for providing a reference voltage which is responsive to a voltage level of an input signal at a logic high and which is at a predetermined voltage when the input signal is at a logic low, comprising: load means coupled between a first power supply terminal and a reference node for providing resistance therebetween; a first transistor having a first current electrode coupled to the reference node, a control electrode for receiving the input signal, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving the input signal, and a second current electrode; and a third transistor having a control electrode and a first current electrode coupled to the second current electrode of the second transistor, and a second current electrode coupled to the second power supply terminal, wherein the second and third transistors are of a conductivity type opposite to that of the first transistor.
Claim 5
Dependent Claim
168 words
A reference voltage generator for providing a reference voltage which is responsive to a voltage level of an input signal at a logic high and which is at a predetermined voltage when the input signal is at a logic low, comprising: load means coupled between a first power supply terminal and a reference node for providing resistance therebetween; a first transistor having a first current electrode coupled to the reference node, a control electrode for receiving the input signal, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving the input signal, and a second current electrode; and a third transistor having a control electrode and a first current electrode coupled to the second current electrode of the second transistor, and a second current electrode coupled to the second power supply terminal, wherein the second and third transistors are of a conductivity type opposite to that of the first transistor.
Claim 6
Dependent Claim
108 words
The reference voltage generator of claim 3, further comprising: a fourth transistor interposed between the reference node and the first current electrode of the first transistor, and having a first current electrode and a control electrode coupled to the reference node, and a second current electrode coupled to the first current electrode of the first transistor; and a fifth transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the reference node, and a second current electrode for providing the reference voltage, wherein the fourth and fifth transistors are of a conductivity type opposite to that of the first transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-02 | 1988-04-02 | 1988-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-02 | 1992-04-02 | 1992-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-02 | 1996-04-02 | 1996-10-02 | $7700.00 | Window Closed / Lapsed |