Patent US6249742B1 successfully refreshed from Google Patents.
US3975649A
Expired / Lapsed
US
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Electronic circuit using field effect transistor with compensation means
Assignee: Hitachi Ltd
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Filing: 1974-03-20
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Granted: 1976-08-17
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Expires: 1994-03-20
Abstract
Abstract In order to provide compensation for changes in the ambient temperature and supply voltage for an electronic circuit, such as a pulse generator circuit made up of MOSIC structure, a field effect transistor circuit includes a high value resistor and an enhancement and depletion type MOSFET, connected in parallel. The drain electrodes of the MOSFETs are connected to the power supply through the resistor and are also connected to the gate electrode of a depletion type load MOSFET which is the load transistor for an enhancement type MOSFET. When the compensating circuit is provided in a pulse generator circuit, instability in the oscillating frequency of the pulse generator due to changes in ambient temperature and supply voltage is overcome and the difference in the oscillating periods for the various MOSICs are decreased.
Inventors
- 👤 Hiroto Kawagoe
- 👤 Kosei Nomiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:36
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/011; H03F; H03F1/00; H03F1/30; H03F1/301; H03F3/00; H03F3/34; H03F3/343; H03F3/345; H03L; H03L1/00; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
117 words
In an electronic circuit having first and second field effect transistors connected in series between a terminal for connecting source of reference potential and a terminal for connecting a power supply source thereto, the improvement comprising a compensating circuit including: a third field effect transistor, the source electrode of which is connected to said reference potential terminal, the gate electrode of which is connected to the source electrode thereof, and the drain electrode of which is connected to the gate electrode of said second field effect transistor; and a resistor, the current flow therethrough being substantially linearly proportional to the voltage drop thereacross, connected between the drain electrode of said third transistor and power supply source terminal.
Claim 2
Dependent Claim
117 words
In an electronic circuit having first and second field effect transistors connected in series between a terminal for connecting source of reference potential and a terminal for connecting a power supply source thereto, the improvement comprising a compensating circuit including: a third field effect transistor, the source electrode of which is connected to said reference potential terminal, the gate electrode of which is connected to the source electrode thereof, and the drain electrode of which is connected to the gate electrode of said second field effect transistor; and a resistor, the current flow therethrough being substantially linearly proportional to the voltage drop thereacross, connected between the drain electrode of said third transistor and power supply source terminal.
Claim 3
Dependent Claim
58 words
The compensating circuit improvement according to claim 1, further comprising a fourth field effect transistor, the drain and source electrodes of which are respectively connected to the drain and source electrodes of said third transistor, and the gate electrode of said fourth transistor is connected to one of the drain electrodes thereof and said power supply source terminal.
Claim 4
Dependent Claim
35 words
The compensating circuit improvement according to claim 2, wherein said first and fourth transistors are enhancement type insulated gate field effect transistors, and said second and third transistors are depletion type gate field effect transistors.
Claim 5
Dependent Claim
144 words
An electronic circuit with compensation means, comprising: a first field effect transistor; a second field effect transistor connected in series with said first field effect transistor; a third field effect transistor, the drain and source electrodes of which are connected to the gate electrode of said second transistor and to the source electrode of said first transistor, respectively; and a resistor, the current flow therethrough being substantially linearly proportional to the voltage drop thereacross, connected between the gate electrode and the drain electrode of said second transistor; wherein the source electrode of said first transistor is connected to a terminal for connecting a source of reference potential thereto and the drain electrode of said second transistor is connected to a terminal for connecting a source of power thereto and wherein the gate electrode of said third transistor is connected to the source electrode thereof.
Claim 6
Dependent Claim
144 words
An electronic circuit with compensation means, comprising: a first field effect transistor; a second field effect transistor connected in series with said first field effect transistor; a third field effect transistor, the drain and source electrodes of which are connected to the gate electrode of said second transistor and to the source electrode of said first transistor, respectively; and a resistor, the current flow therethrough being substantially linearly proportional to the voltage drop thereacross, connected between the gate electrode and the drain electrode of said second transistor; wherein the source electrode of said first transistor is connected to a terminal for connecting a source of reference potential thereto and the drain electrode of said second transistor is connected to a terminal for connecting a source of power thereto and wherein the gate electrode of said third transistor is connected to the source electrode thereof.
Claim 7
Dependent Claim
54 words
The electronic circuit according to claim 4, further comprising a fourth field effect transistor, the drain and source electrodes of which are connected to the drain and source electrodes of said third transistor, respectively, the gage electrode of said fourth transistor being connected to one of the drain electrodes thereof and a power source.
Claim 8
Dependent Claim
39 words
The electronic circuit according to claim 5, wherein said first and fourth transistors are insulated gate field effect transistors of an enhancement type, and said second and third transistors are insulated gate field effect transistors of a depletion type.
Claim 9
Dependent Claim
146 words
In an electronic circuit having first and second field effect transistors connected in series between a terminal for connecting a source of reference potential thereto and a terminal for connecting a power supply source thereto, said second field effect transistor acting as a load for said first effect transistor, the improvement comprising a bias circuit for said second field effect transistor including a resistor, the current flow therethrough being substantially linearly proportional to the voltage drop thereacross, having two terminals, one of which is coupled to said power source terminal, and a third field transistor coupled to said resistor in series between another terminal of said resistor and said reference potential terminal, the gate electrode of said third field effect transistor being coupled to said reference potential terminal, said another terminal of said resistor being coupled to the gate electrode of said second field effect transistor.
Claim 10
Dependent Claim
146 words
In an electronic circuit having first and second field effect transistors connected in series between a terminal for connecting a source of reference potential thereto and a terminal for connecting a power supply source thereto, said second field effect transistor acting as a load for said first effect transistor, the improvement comprising a bias circuit for said second field effect transistor including a resistor, the current flow therethrough being substantially linearly proportional to the voltage drop thereacross, having two terminals, one of which is coupled to said power source terminal, and a third field transistor coupled to said resistor in series between another terminal of said resistor and said reference potential terminal, the gate electrode of said third field effect transistor being coupled to said reference potential terminal, said another terminal of said resistor being coupled to the gate electrode of said second field effect transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-17 | 1980-02-16 | 1980-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-17 | 1984-02-16 | 1984-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-17 | 1988-02-16 | 1988-08-17 | $7700.00 | Window Closed / Lapsed |