US3760199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fet zero temperature-coefficient bias
Assignee: Texas Instruments Tucson Corp
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Filing: 1972-09-11
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Granted: 1973-09-18
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Expires: 1992-09-11
Abstract
Abstract Compensatory circuitry is disclosed for developing biasing voltage sources, which sources are adjusted to conform with temperature sensitive variations and manufacturing variations of junction field effect transistors, and thereby consistently produce a zero temperature coefficient bias. The pinchoff voltage of junction field effect transistors varies with temperature and must be compensated by an equal and opposite compensating voltage. The pinchoff and compensatory voltages are developed and the combination of the two will provide a zero temperature coefficient bias voltage by providing a stable bias to the junction field effect transistor resulting in a drain current equivalent to the drain current at the zero temperature coefficient point.
Inventors
- 👤 J Graeme
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:20
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; H; H03; H03F; H03F1/00; H03F1/30; H03F1/306; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
213 words
Compensatory circuitry for biasing a field effect transistor at the zero temperature coefficient bias, said circuitry comprising in combination: a. a first and second field effect transistor, each said field effect transistor having a drain, a source, and a gate; b. a potential source connected to the gate of said first field effect transistor through a forward semiconductor junction, thE voltage drop across said junction being temperature dependent; c. means for providing feedback between the source and drain of said first field effect transistor; d. means disposed between said junction and the source of said first field effect transistor for developing a temperature dependent voltage; e. a bias potential source disposed between said potential source and the gate of said second field effect transistor, the value of said bias potential source being temperature independent; f. means for biasing the source of said second field effect transistor with the voltage developed across said resistor; and g. an output terminal connected to the drain of said second field effect transistor, whereby the compensatory effect of said bias potential source cooperating with the temperature dependent voltage applied to the source of said second field effect transistor by said biasing means produces an output current at the zero temperature coefficient point of said second field effect transistor.
Claim 2
Dependent Claim
213 words
Compensatory circuitry for biasing a field effect transistor at the zero temperature coefficient bias, said circuitry comprising in combination: a. a first and second field effect transistor, each said field effect transistor having a drain, a source, and a gate; b. a potential source connected to the gate of said first field effect transistor through a forward semiconductor junction, thE voltage drop across said junction being temperature dependent; c. means for providing feedback between the source and drain of said first field effect transistor; d. means disposed between said junction and the source of said first field effect transistor for developing a temperature dependent voltage; e. a bias potential source disposed between said potential source and the gate of said second field effect transistor, the value of said bias potential source being temperature independent; f. means for biasing the source of said second field effect transistor with the voltage developed across said resistor; and g. an output terminal connected to the drain of said second field effect transistor, whereby the compensatory effect of said bias potential source cooperating with the temperature dependent voltage applied to the source of said second field effect transistor by said biasing means produces an output current at the zero temperature coefficient point of said second field effect transistor.
Claim 3
Dependent Claim
21 words
The circuitry as set forth in claim 1, wherein said junction comprises a diode and said developing means comprises a resistor.
Claim 4
Dependent Claim
17 words
The circuitry as set forth in claim 2, wherein said means for providing feedback comprises a transistor.
Claim 5
Dependent Claim
46 words
The circuitry as set forth in claim 3, wherein said transistor includes: a. a base connected to the drain of said field effect transistor; b. a collector connected to the source of said field effect transistor; and c. an emitter connected to a further potential source.
Claim 6
Dependent Claim
27 words
The circuitry as set forth in claim 2, wherein said bias potential source includes a voltage equivalent to the voltage drop across said diode at room temperature.
Claim 7
Dependent Claim
49 words
The circuitry as set forth in claim 3, wherein said transistor includes: a. a base connected to the source of said first field effect transistor; b. an emitter connected to said resistor; c. a collector connected to the drain of said first field effect transistor and another potential source.
Claim 8
Dependent Claim
30 words
The circuitry as set forth in claim 6, wherein said biasing means comprises an emitter follower buffer disposed between said resistor and the source of said second field effect transistor.
Claim 9
Dependent Claim
17 words
The circuitry as set forth in claim 1, wherein said first field effect transistor is in pinchoff.
Claim 10
Dependent Claim
135 words
Compensatory circuitry for biasing a field effect transistor at zero temperature coefficient bias, including a potential source, said circuitry comprising in combination: a. a first and second field effect transistor, each said field effect transistor having a drain, a source, and a gate; b. means for providing feedback between the source and drain of said first field effect transistor to develop a voltage source equal to the pinchoff voltage; c. a compensating bias voltage derived from the forward biased voltage of a semiconductor junction; d. a temperature independent constant voltage bias applied to said second field effect transistor; e. means for combining said pinchoff voltage source with said compensating bias voltage, and said constant voltage bias; whereby the combination produces a voltage which is the zero temperature coefficient bias of said second field effect transistor.
Claim 11
Dependent Claim
135 words
Compensatory circuitry for biasing a field effect transistor at zero temperature coefficient bias, including a potential source, said circuitry comprising in combination: a. a first and second field effect transistor, each said field effect transistor having a drain, a source, and a gate; b. means for providing feedback between the source and drain of said first field effect transistor to develop a voltage source equal to the pinchoff voltage; c. a compensating bias voltage derived from the forward biased voltage of a semiconductor junction; d. a temperature independent constant voltage bias applied to said second field effect transistor; e. means for combining said pinchoff voltage source with said compensating bias voltage, and said constant voltage bias; whereby the combination produces a voltage which is the zero temperature coefficient bias of said second field effect transistor.
Claim 12
Dependent Claim
159 words
The circuitry as set forth in claim 1, wherein: a. said compensating bias voltage is produced by a forward biased diode disposed between the potential source and the gate of said first field effect transistor; b. a resistor is disposed between said diode and the source of said first field effect transistor for developing said pinchoff voltage; c. said constant voltage bias being disposed intermediate the potential source and the gate of said second field effect transistor. d. means for applying the voltage developed across said resistor and said diode at the source of said second field effect transistor; and e. an output terminal connected to the drain of said second field effect transistor, whereby the cOmpensatory effect of said bias potential source cooperating with the temperature dependent voltage applied to the source of said second field effect transistor by said biasing means produces an output current at the zero temperature coefficient point of said second field effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-17 | 1977-03-19 | 1977-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-17 | 1981-03-19 | 1981-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-17 | 1985-03-19 | 1985-09-18 | $7700.00 | Window Closed / Lapsed |