Low-power, tristate, off-chip driver circuit

Claim 2

An output driver circuit for a semiconductor chip, comprising: a) a predriver circuit having a data input, an enable input, a first data output, and a second data output; b) a push, pull out put circuit having an output node for coupling to an off-chip connection, and having first and second inputs, said first input of said output circuit being coupled to receive said first data output of said predriver circuit; c) a first compensator circuit having inputs coupled to said data input, said enable input, and said first data output of said predriver circuit; d) a second compensator circuit having inputs coupled to said data input, said enable input, and said second data output of said predriver circuit; said first and second compensator circuits preventing change of voltage on said first and second inputs of said push-pull output circuit at a rate as high as the rate of change of voltage at said first and second data output; and e) a circuit formed in a well of said semiconductor chip, having an input coupled to receive said second data output of said predriver circuit and having an output coupled to said second input of said push-pull output circuit; said circuit formed in a well preventing damage to said output driver circuit due to overvoltage on said output node.

Claim 3

An output driver circuit for a semiconductor chip, comprising: a) a predriver circuit having a data input, an enable input, a first data output, and a second data output; b) a push-pull output circuit having an output node for coupling to an off-chip connection, and having first and second inputs, said first input of said output circuit being coupled to receive said first data output of said predriver circuit; wherein said push-pull circuit includes a P-channel pull-up transistor and an N-channel Pull-down transistor, said first input of said push-pull output circuit connected to a gate of said P-channel pull-up transistor, said second input of said push-pull output circuit being connected to a gate of said N-channel pull-down transistor; c) a first compensator circuit having inputs coupled to said data input, said enable input, and said first data output of said predriver circuit; and d) a second compensator circuit having inputs coupled to said data input, said enable input, and said second data output of said predriver circuit; said first and second compensator circuits preventing change of voltage on said first and second inputs of said push-pull output circuit at a rate as high as the rate of change of voltage at said first and second data output; and e) a feedback circuit from a drain node of said pull-down transistor to a third input of said first and second compensating circuits, said feedback circuit causing said compensator circuits to cease the compensating function after a selected delay following a transition of the voltage on said output node.

Claim 4

An output driver circuit for a semiconductor chip, comprising: a) a predriver circuit having a data input, an enable input, a first data output, and a second data output; b) a push-pull output circuit having an output node for coupling to an off-chip connection, and having first and second inputs, said first input of said output circuit being coupled to receive said first data output of said predriver circuit; wherein said push-pull circuit includes a P-channel pull-up transistor and an N-channel Pull-down transistor, said first input of said push-pull output circuit connected to a gate of said P-channel pull-up transistor, said second input of said push-pull output circuit being connected to a gate of said N-channel pull-down transistor; c) a first compensator circuit having inputs coupled to said data input, said enable input, and said first data output of said predriver circuit; and d) a second compensator circuit having inputs coupled to said data input, said enable input, and said second data output of said predriver circuit; said first and second compensator circuits preventing change of voltage on said first and second inputs of said push-pull output circuit at a rate as high as the rate of change of voltage at said first and second data output; and e) a feedback circuit from a drain node of said pull-down transistor to a third input of said first and second compensating circuits, said feedback circuit causing said compensator circuits to cease the compensating function after a selected delay following a transition of the voltage on said output node.

Claim 5

An output driver circuit according to claim 2, wherein said first and second compensating circuits each include a plurality of P- and N-channel transistors having source-to-drain paths connected in series.

Claim 6

An output driver circuit according to claim 2, including a stack of diodes connected in a forward direction between the well of said P-channel pull-up transistor and a terminal of a voltage supply.

Claim 7

An output driver circuit according to claim 4, including: a circuit formed in a well of said semiconductor chip, having an input coupled to receive said second data output of said predriver circuit and having an output coupled to said gate of said P-channel pull up transistor of said push-pull output circuit; said circuit formed in a well preventing damage to said output driver circuit due to overvoltage on said output node.

Claim 8

An output driver circuit according to claim 5, wherein one of said diodes is a PN junction of said P-channel pull-up transistor and the remaining one of said diodes are formed in wells separate from said N-well.

Claim 9

An output driver circuit according to claim 6, including a feedback circuit from a drain node of said pull-down transistor to a third input of said first and second compensating circuits, said feedback circuit causing said compensator circuits to cease the compensating function after a selected delay following a transition of the voltage on said output node.

Claim 10

An output driver circuit according to claim 7, wherein said first and second compensating circuits each include a plurality of P- and N-channel transistors having source-to-drain paths connected in series.

Claim 11

A driver circuit comprising: a) a predriver circuit having a data input, and having data output means; b) an output driver circuit having an input coupled to said data output means of said predriver circuit which includes a stack of diodes connected in a forward direction between the output driver circuit and a terminal of a voltage supply; c) a compensation circuit coupled to said predriver circuit and said output driver circuit; d) clamping means, coupled to said driver circuit, for limiting the voltage to which said circuits in said driver circuit may be exposed during operation.

Claim 12

A driver circuit comprising: a) a predriver circuit having a data input, and having data output means; b) an output driver circuit having an input coupled to said data output means of said predriver circuit which includes a stack of diodes connected in a forward direction between the output driver circuit and a terminal of a voltage supply; c) a compensation circuit coupled to said predriver circuit and said output driver circuit; d) clamping means, coupled to said driver circuit, for limiting the voltage to which said circuits in said driver circuit may be exposed during operation.

Claim 13

An output driver circuit according to claim 9, including: a circuit formed in a well of a semiconductor chip containing said output driver circuit, having an input coupled to said data output means of said predriver circuit and having an output coupled to said input of said output driver circuit: said circuit formed in a well preventing damage to said output driver circuit due to overvoltage on said output node.

Claim 14

An output driver circuit according to claim 10, wherein said output driver circuit includes a P-channel pull-up transistor and an N-channel pull-down transistor said input of said output driver circuit including a gate of said P-channel pull-up transistor and a gate of said N-channel pull-down transistor.

Claim 15

An output driver circuit according to claim 11, including a feedback circuit from a drain node of said pull-down transistor to another input of said compensating circuit, said feedback circuit causing said compensator circuit to cease the compensating function after a selected delay following a transition of the voltage on said output node.

Claim 16

An output driver circuit according to claim 12, wherein said compensating circuit includes a plurality of P- and N-channel transistors having source-to-drain paths connected in series.

Claim 17

An output driver circuit according to claim 13, wherein said plurality of P- and N-channel transistors of said compensating circuit, includes, in order from said terminal of said supply to a gate of a compensating transistor: a P-channel transistor having a gate connected to said data input; an N-channel transistor having a gate connected to an enable input; an N-channel transistor having a gate connected to said another input of said compensating circuit.