US4477741A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic output impedance for 3-state drivers
Assignee: International Business Machines Corp
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Filing: 1982-03-29
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Granted: 1984-10-16
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Expires: 2002-03-29
Abstract
Abstract This describes a tristate driver circuit designed such that it will not be destroyed by excessive high voltage conditions when two such drivers are connected to a bus at the same time. The circuit accomplishes this with parallel high current, low impedance and low current, high impedance output devices, coupled to means for causing the high current, low impedance devices to supply, to the circuit output, only the initial high currents required without inhibiting the low current, high impedance devices from maintaining the steady state conditions needed to clamp the output at the desired output level. The circuit is arranged to cause both high and low current output devices to be initially conductive to charge the output terminal to the desired level, but to subsequently shut off the high current, low impedance device while keeping the low current, high impedance device in a condition to clamp the output at the desired level. This result is achieved by providing the high current output devices with means for automatically terminating once the initially required high current has been supplied to the output.
Inventors
- 👤 John J. Moser, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K19/003; H03K19/00315; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
332 words
A driver circuit comprising: an input signal means, first, second, third, fourth, fifth, sixth and seventh field effect transistors, each having a drain electrode, a source electrode and a control electrode, the first transistor having its drain electrode coupled to a voltage source through a load device, its source electrode coupled to ground, and its control electrode coupled to said input signal means, the second transistor having its control electrode coupled to said input signal means, its drain electrode coupled to said voltage source and its source electrode connected to a capacitive load, the third transistor in parallel with said second transistor, the drain electrode of said third transistor coupled to said voltage source and its source connected to said load, and its control electrode coupled to the control electrode of the second transistor through a capacitor and to ground through a resistor to change the voltage on the control electrode of said third transistor a preselected time after a signal is applied thereto, the fourth transistor having its control electrode connected to the drain electrode of the first transistor, its drain electrode coupled to the load, and its source connected to ground, the fifth transistor having its drain electrode connected to the load, its source electrode connected to ground, and its control electrode coupled to the control electrode of the fourth transistor through a capacitor and to ground through a resistor to change the voltage on the control electrode of said fifth transistor a preselected time after a signal is applied thereto, the control electrodes of said sixth and seventh transistors being coupled to a disable input, the drain of the sixth transistor being coupled to the control electrode of said second transistor, and the drain of said seventh transistor being coupled to the control electrode of said fourth transistor and their sources being coupled to ground whereby turning on of said sixth and seventh transistors grounds the control electrodes of said second and fourth transistors thereby isolating said capacitive load.
Claim 2
Dependent Claim
332 words
A driver circuit comprising: an input signal means, first, second, third, fourth, fifth, sixth and seventh field effect transistors, each having a drain electrode, a source electrode and a control electrode, the first transistor having its drain electrode coupled to a voltage source through a load device, its source electrode coupled to ground, and its control electrode coupled to said input signal means, the second transistor having its control electrode coupled to said input signal means, its drain electrode coupled to said voltage source and its source electrode connected to a capacitive load, the third transistor in parallel with said second transistor, the drain electrode of said third transistor coupled to said voltage source and its source connected to said load, and its control electrode coupled to the control electrode of the second transistor through a capacitor and to ground through a resistor to change the voltage on the control electrode of said third transistor a preselected time after a signal is applied thereto, the fourth transistor having its control electrode connected to the drain electrode of the first transistor, its drain electrode coupled to the load, and its source connected to ground, the fifth transistor having its drain electrode connected to the load, its source electrode connected to ground, and its control electrode coupled to the control electrode of the fourth transistor through a capacitor and to ground through a resistor to change the voltage on the control electrode of said fifth transistor a preselected time after a signal is applied thereto, the control electrodes of said sixth and seventh transistors being coupled to a disable input, the drain of the sixth transistor being coupled to the control electrode of said second transistor, and the drain of said seventh transistor being coupled to the control electrode of said fourth transistor and their sources being coupled to ground whereby turning on of said sixth and seventh transistors grounds the control electrodes of said second and fourth transistors thereby isolating said capacitive load.
Claim 3
Dependent Claim
21 words
The device of claim 1 wherein said load device comprises: a field effect transistor having its gate coupled to its drain.
Claim 4
Dependent Claim
276 words
A trilevel driver circuit comprising: an input signal means, a signal inverter means connected to said input means for providing at its output an inverted input signal, first and second push-pull transistor pairs, one of said pairs comprising two serially arranged high impedance transistors and the other of said pairs comprising two serially arranged low impedance transistors, a capacitively loaded output means coupled to both of said push-pull pairs of transistors, one of said high impedance transistors having its control element connected to the signal input means and the other of said high impedance transistors having its control element connected to the output of said inverter, a first capacitor means coupling the control element of the first one of said low impedance transistors to the control element of the first one of said high impedance transistors, a first resistor connecting the control element of said first one of said low impedance transistors to ground, a second capacitor means coupling the control element of the second one of said low impedance transistors to the control element of the second one of said high impedance transistors and a second resistor connecting the control element of said second one of said low impedance transistors to ground for altering the signals applied to said low impedance transistors without altering the signals applied to said high impedance transistors, and disabling means coupled to the control elements of said high impedance transistors for grounding said control elements and causing said high impedance transistors to turn off to prevent said output from being clamped to a voltage and permiting said output means to float dependent on the capacitive load on said output means.
Claim 5
Dependent Claim
276 words
A trilevel driver circuit comprising: an input signal means, a signal inverter means connected to said input means for providing at its output an inverted input signal, first and second push-pull transistor pairs, one of said pairs comprising two serially arranged high impedance transistors and the other of said pairs comprising two serially arranged low impedance transistors, a capacitively loaded output means coupled to both of said push-pull pairs of transistors, one of said high impedance transistors having its control element connected to the signal input means and the other of said high impedance transistors having its control element connected to the output of said inverter, a first capacitor means coupling the control element of the first one of said low impedance transistors to the control element of the first one of said high impedance transistors, a first resistor connecting the control element of said first one of said low impedance transistors to ground, a second capacitor means coupling the control element of the second one of said low impedance transistors to the control element of the second one of said high impedance transistors and a second resistor connecting the control element of said second one of said low impedance transistors to ground for altering the signals applied to said low impedance transistors without altering the signals applied to said high impedance transistors, and disabling means coupled to the control elements of said high impedance transistors for grounding said control elements and causing said high impedance transistors to turn off to prevent said output from being clamped to a voltage and permiting said output means to float dependent on the capacitive load on said output means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-16 | 1988-04-16 | 1988-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-16 | 1992-04-16 | 1992-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-16 | 1996-04-16 | 1996-10-16 | $7700.00 | Window Closed / Lapsed |