High capacitance driving circuit

Claim 2

A driver circuit for supplying signals to a high-capacitance load, said circuit comprising an input terminal for receiving an input signal at one of two levels, and an output terminal, first and second switch means operatively connected to said input terminal, third and fourth switch means respectively operatively connected to said first and second switch means and to said output terminal, first and second sources of signals at first and second levels, said third and fourth switch means being effective when actuated to respectively charge said output terminal to said first and second levels, said first and second switch means being selectively alternately actuated at different levels of said input signal and effective when so actuated to respectively actuate one of said third and fourth switch means, and means operatively connected to said first and second switch means and effective after one of said first and second switch means is actuated and while it remains actuated to respectively reduce the actuating signal to said third and fourth switch means.

Claim 3

The circuit of claim 1, further comprising fifth and sixth switch means respectively operatively connected to said third and fourth switch means, said first and second signal sources, and said output terminals, and respectively actuated upon the actuation of said third and fourth switch means to operatively connect said output terminal to one of said signal sources, and respectively deactuated when the drive to said third and fourth switch means is reduced from one of said first and second switch means in response to the action of said reducing means, said output terminal thereafter remaining in operative connection to one of said signal sources through one of said third and fourth switch means.

Claim 4

The circuit of claim 2, in which said drive reducing means comprises charging means operatively connected to said first and second switch means, initially at a first level, and chargeable to a second level after said one of said first and second switch means is actuated to reduce the actuating signal to said one of said first and second switch means.

Claim 5

The circuit of claim 3, in which said fifth and sixth switch means are each relatively high-current and low switching speed devices, and said third and fourth switching devices are each relatively low-current, and high-speed switching devices.

Claim 6

The circuit of claim 4, further comprising first and second control means respectively operatively connected to said third, and fifth switch means, and third and fourth control means respectively operatively connected to said fourth and sixth switch means, said first and third control means being respectively effective to maintain one of said third and fourth switch means conductive, and said second and fourth control means being effective to render non-conductive the previously actuated one of said fifth and sixth switch means after the actuating signal is reduced to one of said third and fourth switch means.

Claim 7

The circuit of claim 5, in which said third and fifth switch means are transistors of one type, and said fourth and sixth switch means are transistors of an opposite conductivity type said transistors having emitter and base terminals, said first and third control means comprising first and third resistors of a first value of resistance respectively operatively connected between the base and emitter terminals of said third and fourth switch means, said second and fourth control means comprising second and fourth resistors of a second value of resistance lower than said first value of resistance, and respectively operatively connected between the emitters of said third and fifth switch means and said fourth and sixth switch means.

Claim 8

The circuit of claim 6, in which said first and third resistors are operatively connected in series between said first signal source and said first switch means, and said second and fourth resistors are operatively connected in series between said signal source and said second switch means.

Claim 9

The circuit of claim 2, in which said fifth and sixth switch means are each relatively high-current and low switching speed devices, and said third and fourth switching devices are each relatively low-current, and high-speed switching devices.

Claim 10

The circuit of claim 8, further comprising first and second control means respectively operatively connected to the control terminals of said third, and fifth switch means, and third and fourth control means respectively operatively connected to the control terminals of said fourth and sixth switch means, said first and third control means being respectively effective to maintain one of said third and fourth switch means conductive, and said second and fourth control means being effective to render nonconductive the previously actuated one of said fifth and sixth switch means after the actuating signal is reduced to one of said third and fourth switch means.

Claim 11

The circuit of claim 9, in which said third and fifth switch means are transistors of one type, and said fourth and sixth switch means are transistors of an opposite conductivity type said transistors having emitter and base terminals, said first and third control means comprising first and third resistors of a first value of resistance respectively operatively connected between the base and emitter terminals of said third and fourth switch means, said second and fourth control means comprising second and fourth resistors of a second value of resistance lower than said first value of resistance, and respectively operatively connected between the emItters of said third and fifth switch means and said fourth and sixth switch means.

Claim 12

The circuit of claim 10, in which said first and third resistors are operatively connected in series between said first signal source and said first switch means, and said second and fourth resistors are operatively connected in series between said signal source and said second switch means.

Claim 13

The circuit of claim 1, in which said drive reducing means comprises charging means operatively connected to said first and second switch means, initially at a first level, and chargeable to a second level after said one of said first and second switch means is actuated to reduce the actuating signal to said one of said first and second switch means.

Claim 14

The circuit of claim 2, further comprising first and second control means respectively operatively connected to the control terminals of said third and fifth switch means, and third and fourth control means respectively operatively connected to the control terminals of said fourth and sixth switch means, said first and third control means being respectively effective to maintain one of said third and fourth switch means conductive, and said second and fourth control means being effective to render nonconductive the previously actuated one of said fifth and sixth switch means after the actuating signal is reduced to one of said third and fourth switch means.

Claim 15

The circuit of claim 2, further comprising first and second control means respectively operatively connected to said third, and fifth switch means, and third and fourth control means respectively operatively connected to said fourth and sixth switch means, said first and third control means being respectively effective to maintain one of said third and fourth switch means conductive, and said second and fourth control means being effective to render nonconductive the previously actuated one of said fifth and sixth switch means after the actuating signal is reduced to one of said third and fourth switch means, and in which said third and fifth switch means are transistors of one type, and said fourth and sixth switch means are transistors of an opposite conductivity type, said transistors having base and emitter terminals, said first and third control means comprising first and third resistors of a first value of resistance respectively operatively connected between the base and emitter terminals of said third and fourth switch means, said second and fourth control means comprising second and fourth resistors of a second value of resistance lower than said first value of resistance, and respectively operatively connected between the emitters of said third and fifth switch means and said fourth and sixth switch means.

Claim 16

A driver circuit for supplying signals at one of two levels to a high-capacitance load, said circuit comprising an input and an output terminal, first switch means operatively connected to said input terminal and actuated when said input signal is at one of its said levels, a source of a reference signal, second switch means operatively connected to said first switch means and said output terminal, third switch means operatively connected to said second switch means and said output terminal, said second and third switch means being actuated when said first switch means is initially actuated and effective when so actuated to operatively connect said reference signal source to said output terminal, and means operatively connected to said first switch means and effective after said first switch means is initially actuated and while it remains actuated to reduce the output of said first switch means and thereby deactuate one of said second and third switch means.

Claim 17

A driver circuit for supplying signals at one of two levels to a high-capacitance load, said circuit comprising an input and an output terminal, first switch means operatively connected to said input terminal and actuated when said input signal is at one of its said levels, a source of a reference signal, second switch means operatively connected to said first switch means and said output terminal, third switch means operatively connected to said second switch means and said output terminal, said second and third switch means being actuated when said first switch means is initially actuated and effective when so actuated to operatively connect said reference signal source to said output terminal, and means operatively connected to said first switch means and effective after said first switch means is initially actuated and while it remains actuated to reduce the output of said first switch means and thereby deactuate one of said second and third switch means.

Claim 18

The circuit of claim 15, in which said one of said second and third switch means is a relatively high-current, low switching speed device, and the other of said second and third switch means is a relatively low-current and high-speed device.

Claim 19

The circuit of claim 16, in which said drive reducIng means comprises charging means operatively connected to said first switch means, and chargeable from a first to a second level when said first switch means is actuated, and effective when at said second level to reduce the actuating signal to said first switch means.

Claim 20

The circuit of claim 17, further comprising first and second control means operatively connected to said second and third switch means, and effective to maintain the former conductive and to render the latter nonconductive when the drive from said first switch means is reduced.

Claim 21

The circuit of claim 18, in which said second and third switch means are transistors of a common conductivity type said transistors having emitter and base terminals, said first and second control means comprising first and second resistor means respectively operatively connected to the emitter and base terminals of said second and third switch means, said first resistor means having a higher value of resistance as compared to that of said second resistor means.

Claim 22

The circuit of claim 19, in which said first and second resistor means are in operative series connection between said source and said first switch means.

Claim 23

The circuit of claim 15, in which said drive reducing means comprises charging means operatively connected to said first switch means, and chargeable from a first to a second level when said first switch means is actuated, and effective when at said second level to reduce the actuating signal to said first switch means.

Claim 24

The circuit of claim 21, further comprising first and second control means operatively connected to said second and third switch means, and effective to maintain the former conductive and to render the latter nonconductive when the drive from said first switch means is reduced.

Claim 25

The circuit of claim 22, in which said second and third switch means are transistors of a common conductivity type said transistors having emitter and base terminals, said first and second control means comprising first and second resistor means respectively operatively connected to the emitter and base terminals of said second and third switch means, said first resistor means having a higher value of resistance as compared to that of said second resistor means.

Claim 26

The circuit of claim 16, further comprising first and second control means operatively connected to said second and third switch means, and effective to maintain the former conductive and to render the latter nonconductive when the drive from said first switch means is reduced, and in which said second and third switch means are transistors of a common conductivity type, said transistors having base and emitter terminals, said first and second control means comprising first and second resistor means respectively operatively connected to the emitter and base terminals of said second and third switch means, said first resistor means having a higher value of resistance as compared to that of said second resistor means.

Claim 27

The circuit of claim 24, in which said first and second resistor means are in operative series connection between said source and said first switch means.

Claim 28

The circuit of claim 15, further comprising first and second control means operatively connected to terminals of said second and third switch means, and effective to maintain the former conductive and to render the latter nonconductive when the drive from said first switch means is reduced.

Claim 29

The circuit of claim 26, in which said second and third switch means are transistors of a common conductivity type, said transistors having emitter and base terminals, said first and second control means comprising first and second resistor means respectively operatively connected to the emitter and base terminals of said second and third switch means, said first resistor means having a higher value of resistance as compared to that of said second resistor means.

Claim 30

The circuit of claim 27, in which said first and second resistor means are in operative seRies connection between said source and said first switch means.