US4291242A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Driver circuit for use in an output buffer
Assignee: Motorola Solutions Inc
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Filing: 1979-05-21
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Granted: 1981-09-22
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Expires: 1999-05-21
Abstract
Abstract A high speed, low power clocked driver circuit is provided. DC paths from voltage V DD to ground is eliminated by carefully clocking field effect transistors within the driver circuit. By using bootstrapping techniques, the output of the circuit approaches V DD . Two of the high speed, low power driver circuits are combined to drive a ratioless output circuit in order to provide an output buffer circuit having a TTL compatible output.
Inventors
- 👤 Gene A. Schriber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
453 words
A high speed driver circuit having field effect transistors and a first and a second voltage node, comprising: a first pair of transistors connected in series between the first and second voltage nodes and having a first and a second control electrode and having an output node formed between the first pair of transistors, the first control electrode being coupled to a clocking signal, the second control electrode being coupled to a precharge signal; a second pair of transistors coupled in series between the first and second voltage nodes and having a first and a second control electrode and providing an output, the first control electrode being coupled to the precharge signal and the second control electrode being coupled to the output of the first pair of transistors; a third pair of transistors coupled between an enable signal input and the output of the second pair of transistors and having a first and a second control electrode and providing an output, the first control electrode being coupled to the precharge signal and the second control electrode being coupled to the clocking signal; an inverter having an input and an output, the input being coupled to the enable signal input; a fourth pair of transistors coupled between the first and second voltage nodes and having a first and a second control electrode and an output, the second control electrode being coupled to the output of the second pair of transistors; a fifth pair of transistors coupled between the clocking signal and the second voltage node and having a first and a second control electrode and an output, the first control electrode being coupled to the output of the third pair of transistors and the second control electrode being coupled to the output of the inverter, the output of the fifth pair of transistors being coupled to the first control electrode of the fourth pair of transistors; capacitor means coupled between the output of the fourth pair of transistors and the first control electrode of the fourth pair of transistors; a first transistor coupled from the output of the third pair of transistors and the second voltage node and having a control electrode coupled to the output of the inverter; a sixth pair of transistors coupled between the first and second voltage nodes and having a first and a second control electrode and an output, the first control electrode being coupled to the output of the fifth pair of transistors, the second control electrode being coupled to the output of the second pair of transistors; and a second transistor coupled between the output of sixth pair of transistors and the second voltage node and having a control electrode coupled to the output of the inverter.
Claim 2
Dependent Claim
453 words
A high speed driver circuit having field effect transistors and a first and a second voltage node, comprising: a first pair of transistors connected in series between the first and second voltage nodes and having a first and a second control electrode and having an output node formed between the first pair of transistors, the first control electrode being coupled to a clocking signal, the second control electrode being coupled to a precharge signal; a second pair of transistors coupled in series between the first and second voltage nodes and having a first and a second control electrode and providing an output, the first control electrode being coupled to the precharge signal and the second control electrode being coupled to the output of the first pair of transistors; a third pair of transistors coupled between an enable signal input and the output of the second pair of transistors and having a first and a second control electrode and providing an output, the first control electrode being coupled to the precharge signal and the second control electrode being coupled to the clocking signal; an inverter having an input and an output, the input being coupled to the enable signal input; a fourth pair of transistors coupled between the first and second voltage nodes and having a first and a second control electrode and an output, the second control electrode being coupled to the output of the second pair of transistors; a fifth pair of transistors coupled between the clocking signal and the second voltage node and having a first and a second control electrode and an output, the first control electrode being coupled to the output of the third pair of transistors and the second control electrode being coupled to the output of the inverter, the output of the fifth pair of transistors being coupled to the first control electrode of the fourth pair of transistors; capacitor means coupled between the output of the fourth pair of transistors and the first control electrode of the fourth pair of transistors; a first transistor coupled from the output of the third pair of transistors and the second voltage node and having a control electrode coupled to the output of the inverter; a sixth pair of transistors coupled between the first and second voltage nodes and having a first and a second control electrode and an output, the first control electrode being coupled to the output of the fifth pair of transistors, the second control electrode being coupled to the output of the second pair of transistors; and a second transistor coupled between the output of sixth pair of transistors and the second voltage node and having a control electrode coupled to the output of the inverter.
Claim 3
Dependent Claim
70 words
The high speed driver circuit of claim 1 being coupled with a second high speed driver and an output inverter to form an output buffer, the output inverter having a first and a second control electrode, the first control electrode being coupled to the output of the high speed driver circuit of claim 1 and the second control electrode being coupled to the output of the second high speed driver.
Claim 4
Dependent Claim
222 words
A high speed driver circuit having inputs for receiving a clocking signal, a precharge signal, and an enable signal, also having a first and a second voltage node, comprising: a first node; first means coupled between the enable signal input and the first node for precharging the first node; second means coupled to the first node and being enabled by the precharge signal and the clocking signal to discharge the first node; an inverter coupled to the enable signal input for providing an inverted enable signal output; third means coupled to the first node for maintaining the first node in a discharged condition when the third means is enabled by the output of the inverter; a second node; fourth means coupled to the second node for precharging the second node; fifth means having an output coupled to the second node for boosting the precharging of the second node, the fifth means having an input coupled to the second means; sixth means coupled to the second node for discharging the second node when the sixth means is enabled by the output of the inverter; and output means providing an output for the high speed driver circuit and having a first and a second input, the first input being coupled to the second node and the second input being coupled to the second means.
Claim 5
Dependent Claim
222 words
A high speed driver circuit having inputs for receiving a clocking signal, a precharge signal, and an enable signal, also having a first and a second voltage node, comprising: a first node; first means coupled between the enable signal input and the first node for precharging the first node; second means coupled to the first node and being enabled by the precharge signal and the clocking signal to discharge the first node; an inverter coupled to the enable signal input for providing an inverted enable signal output; third means coupled to the first node for maintaining the first node in a discharged condition when the third means is enabled by the output of the inverter; a second node; fourth means coupled to the second node for precharging the second node; fifth means having an output coupled to the second node for boosting the precharging of the second node, the fifth means having an input coupled to the second means; sixth means coupled to the second node for discharging the second node when the sixth means is enabled by the output of the inverter; and output means providing an output for the high speed driver circuit and having a first and a second input, the first input being coupled to the second node and the second input being coupled to the second means.
Claim 6
Dependent Claim
48 words
The high speed driver circuit of claim 3 further including seventh means coupled to the output means and having an input coupled to the output of the inverter to maintain the output in a static state when the seventh means is enabled by the output of the inverter.
Claim 7
Dependent Claim
67 words
The high speed driver circuit of claim 3 further including a second high speed driver circuit and a pair of transistors coupled in series between the first and second voltage nodes and having a first and a second input, the first input being coupled to the output of the output means and the second input being coupled to the output of the second high speed driver circuit.
Claim 8
Dependent Claim
23 words
The circuit of claim 5 wherein the enable signal input of the second high speed driver circuit is coupled to the inverter output.
Claim 9
Dependent Claim
92 words
The circuit of claim 6 further including a first depletion type transistor having a gate, a source, and a drain, the drain being coupled to the first voltage node, the source being coupled to the first input of the pair of transistors, the gate being coupled to the source; and a second depletion type transistor having a gate, a drain and a source coupled to the gate and to the second input of the pair of transistors, the drain of the second depletion type transistor being coupled to the first voltage node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |