Low power output buffer circuit for multiphase systems

Claim 2

A buffer circuit for use in a system using a multiphase clock cycle and having an input terminal for receiving voltage levels representing logic states and an output terminal, said circuit comprising, first and second switching devices having a common connection to said output terminal for setting said output terminal to voltage levels representing the logic states of the voltage levels on said input terminal, first control means including a first storage capacitor means for rendering said first switching device conductive during one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a first logic state, said first control means including means for storing a charge on said first storage capacitor means representing said first logic state and for isolating said first storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said first switching device, second control means including a second storage capacitor means for rendering said second switching device conductive during said one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a second logic state, said second control means including means for storing a charge on said second storage capacitor means and for isolating said second storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said second switching device.

Claim 3

A buffer circuit for use in a system using a multiphase clock cycle and having an input terminal for receiving voltage levels representing logic states and an output terminal, said circuit comprising, first and second switching devices having a common connection to said output terminal for setting said output terminal to voltage levels representing the logic states of the voltage levels on said input terminal, first control means including a first storage capacitor means for rendering said first switching device conductive during one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a first logic state, said control means including means for storing a charge on said first storage capacitor means representing said first logic state and for isolating said first storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said first switching device, second control means including a second storage capacitor means for rendering said second switching device conductive during said one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a second logic state, said second control means including means for storing a charge on said second storage capacitor means and for isolating said second storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said second switching device, said means for storing a charge On said first and second storage capacitor means including means for charging said first and second storage capacitor means to a voltage level representing a first logic state and during a first phase time of said multiphase clock cycle, and said second control means including field effect transistor means for discharging said second storage capacitor means to a voltage level representing said second logic state if said input terminal is set to a voltage level representing said first logic state during a second phase time of said multiphase clock cycle, said second phase time occurring prior to said one recited phase, said first control means including field effect transistor means for discharging said first storage capacitor means to a voltage level representing said second logic state if said input terminal is set to a voltage level representing said second logic state during said second phase time of said multiphase clock cycle.

Claim 4

A buffer circuit for use in a system using a multiphase clock cycle and having an input terminal for receiving voltage levels representing logic states and an output terminal, said circuit comprising, first and second switching devices having a common connection to said output terminal for setting said output terminal to voltage levels representing the logic states of the voltage levels on said input terminal, first control means including a first storage capacitor means for rendering said first switching device conductive during one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a first logic state, said control means including means for storing a charge on said first storage capacitor means representing said first logic state and for isolating said first storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said first switching device, second control means including a second storage capacitor means for rendering said second switching device conductive during said one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a second logic state, said second control means including means for storing a charge on said second storage capacitor means and for isolating said second storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said second switching device, said means for storing a charge On said first and second storage capacitor means including means for charging said first and second storage capacitor means to a voltage level representing a first logic state and during a first phase time of said multiphase clock cycle, and said second control means including field effect transistor means for discharging said second storage capacitor means to a voltage level representing said second logic state if said input terminal is set to a voltage level representing said first logic state during a second phase time of said multiphase clock cycle, said second phase time occurring prior to said one recited phase, said first control means including field effect transistor means for discharging said first storage capacitor means to a voltage level representing said second logic state if said input terminal is set to a voltage level representing said second logic state during said second phase time of said multiphase clock cycle.

Claim 5

A buffer circuit for use in a system using a multiphase clock cycle and having an input terminal for receiving voltage levels representing logic states and an output terminal, said circuit comprising, first and second switching devices having a common connection to said output terminal for setting said output terminal to voltage levels representing the logic states of the voltage levels on said input terminal, first control means including a first storage capacitor means for rendering said first switching device conductive during one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a first logic state, said first control means including means for storing a charge on said first storage capacitor means representing said first logic state and for isolating said first storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said first switching device, second control means including a second storage capacitor means for rendering said second switching device conductive during said one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a second logic state, said second control means including means for storing a charge on said second storage capacitor means and for isolating said second storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said second switching device, said means for storing a charge on said second storage capacitor means including a first field effect transistor connected between said second storage capacitor means and a voltage source for providing a voltage level representing said first logic state during a first phase time of said multiphase clock cycle, and said means for isolating said second storage capacitor means comprising a second field effect transistor connected between said capacitor means and a voltage source for providing a voltage level representing said second logic state during a second phase time of said multiphase clock cycle prior to said recited one interval if said input terminal is set to a voltage level representing said second logic state, said second field effect transistor having a gate electrode connected to said input terminal.

Claim 6

A buffer circuit for use in a system using a multiphase clock cycle and having an input terminal for receiving voltage levels representing logic states and an output terminal, said circuit comprising, first and second switching devices having a common connection to said output terminal for setting said output terminal to voltage levels representing the logic states of the voltage levels on said input terminal, first control means including a first storage capacitor means for rendering said first switching device conductive during one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a first logic state, said first control means including means for storing a charge on said first storage capacitor means representing said first logic state and for isolating said first storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said first switching device, second control means including a second storage capacitor means for rendering said second switching device conductive during said one phase time of said multiphase clock cycle if said input terminal is set to a voltage level representing a second logic state, said second control means including means for storing a charge on said second storage capacitor means and for isolating said second storage capacitor means from said input terminal prior to said one phase, said stored charge enabling the conduction of said second switching device, said means for storing a charge on said second storage capacitor means including a first field effect transistor connected between said second storage capacitor means and a voltage source for providing a voltage level representing said first logic state during a first phase time of said multiphase clock cycle, and said means for isolating said second storage capacitor means comprising a second field effect transistor connected between said capacitor means and a voltage source for providing a voltage level representing said second logic state during a second phase time of said multiphase clock cycle prior to said recited one interval if said input terminal is set to a voltage level representing said second logic state, said second field effect transistor having a gate electrode connected to said input terminal.

Claim 7

A low power push-pull driver circuit used as a buffer stage between a common input terminal and a common output terminal of a multiphase system, said driver comprising two push-pull output field effect transistors of like conductivity type for setting said output terminal to voltage potentials representing first and second logic states as a function of voltage potentials on the input terminal, first means for driving one of said field effect transistors in response to a first voltage potential on said input terminal for connecting said output terminal to a voltage representing a first logic state, and second means for driving said second field effect transistor in response to second voltage potentiaL on said input terminal for setting said output terminal to a voltage representing said second logic state, said second means including an inverter stage comprising field effect transistor switching devices operated in a ratioless manner, said first and second means being electrically separated from each other between said common input and output terminals.

Claim 8

A low power push-pull driver circuit used as a buffer stage between a common input terminal and a common output terminal of a multiphase system, said driver comprising two push-pull output field effect transistors of like conductivity type for setting said output terminal to voltage potentials representing first and second logic states as a function of voltage potentials on the input terminal, first means for driving one of said field effect transistors in response to a first voltage potential on said input terminal for connecting said output terminal to a voltage representing a first logic state, and second means for driving said second field effect transistor in response to second voltage potentiaL on said input terminal for setting said output terminal to a voltage representing said second logic state, said second means including an inverter stage comprising field effect transistor switching devices operated in a ratioless manner, said first and second means being electrically separated from each other between said common input and output terminals.

Claim 9

A low power buffer circuit for use with a multiphase system having first and second field effect transistors operated in a push-pull manner between first and second voltage levels and having a common output terminal, said circuit including an input terminal and comprising, a first control channel between said first field effect transistor and said input terminal, said first control channel including a third field effect transistor connected between the gate electrode of said first field effect transistor and a clock signal, a first storage and feedback capacitor connected between the gate electrode of said third field effect transistor and the gate electrode of said first field effect transistor, said first control channel further including a clocked inverter stage connected between the gate electrode of said third field effect transistor and said input terminal for inverting voltage levels on said input terminal and providing the inverted voltage levels to the gate electrode of said third field effect transistor, a second control channel connected between the gate electrode of said second field effect transistor and said input terminal, said second channel including a fourth field effect transistor connected between the gate electrode of said second field effect transistor and a clock signal, a second storage and feedback capacitor connected between the gate electrode of said fourth field effect transistor and the gate electrode of said second field effect transistor, said second channel further including a clocked fifth field effect transistor connected between said fourth field effect transistor and said input terminal for sampling voltage levels on said input terminal.

Claim 10

A low power buffer circuit for use with a multiphase system having first and second field effect transistors operated in a push-pull manner between first and second voltage levels and having a common output terminal, said circuit including an input terminal and comprising, a first control channel between said first field effect transistor and said input terminal, said first control channel including a third field effect transistor connected between the gate electrode of said first field effect transistor and a clock signal, a first storage and feedback capacitor connected between the gate electrode of said third field effect transistor and the gate electrode of said first field effect transistor, said first control channel further including a clocked inverter stage connected between the gate electrode of said third field effect transistor and said input terminal for inverting voltage levels on said input terminal and providing the inverted voltage levels to the gate electrode of said third field effect transistor, a second control channel connected between the gate electrode of said second field effect transistor and said input terminal, said second channel including a fourth field effect transistor connected between the gate electrode of said second field effect transistor and a clock signal, a second storage and feedback capacitor connected between the gate electrode of said fourth field effect transistor and the gate electrode of said second field effect transistor, said second channel further including a clocked fifth field effect transistor connected between said fourth field effect transistor and said input terminal for sampling voltage levels on said input terminal.

Claim 11

The circuit recited in claim 5 wherein said clocked inverter state includes a sixth field effect transistor for charging said first storage and feedback capacitor to a first voltage level during a first phase time of said multiphase clock cycle, and a seventh field effect transistor for discharging said capacitor to said second voltage level if the voltage level on said input terminal is the first voltage level during a subsequent phase time of said multiphase clocking cycle.

Claim 12

The circuit recited in claim 6 including means for providing a first voltage level at said input terminal during a first phase time of said multiphase clock cycle and means for rendering said clocked fifth field effect transistor conductive and said seventh field effect transistor on during said first phase time for charging said first and second capacitors to said first voltage level during said first phase time, said clocked fifth field effect transistor remaining conductive during a second phase time of said multiphase clock cycle for enabling said second capacitor to discharge to said second voltage level if the voltage level on the input terminal changes to said second voltage level during said second phase time.