Patent US3459615A successfully refreshed from Google Patents.
Patent US2660539A successfully refreshed from Google Patents.
US3868657A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peripheral circuitry for dynamic mos rams
Assignee: Motorola Solutions Inc
•
Filing: 1973-11-19
•
Granted: 1975-02-25
•
Expires: 1993-11-19
Abstract
Abstract Improved circuits for a dynamic MOS RAM having a storage array of inverting storage cells, including an improved input buffer, an improved write circuit, and a sense circuit. The input buffer circuit includes a dynamic latch circuit clocked by the first clock complement signal and is compatible with TTL logic levels. The cross coupled gate nodes of the dynamic latch are conditionally discharged by circuitry which includes a ratio type first address inverter, and a second ratio type address inverter followed by a third ratioless inverter, whose output conditionally discharges one of the cross coupled gate nodes of the dynamic latch. A separate write circuit drives each digitsense column bus line, and includes a push-pull driver clocked by the third clock input signal. The pull-up and pull-down field effect transistors of the push-pull driver each have an exclusive OR type circuit for conditionally discharging the prepcharged gate electrodes of the pull-up and pull-down field effect transistors, depending on the voltages on the data input signal and the data control signal. The ratioless data control inverter and the data input inverter provide the complement signals required by the two exclusive OR type circuits.
Inventors
- 👤 Charles Robert Hoffman
- 👤 Donald H Kube
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:18
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C11/403; G11C11/405; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
168 words
In a monolithic dynamic random access memory connected to first, second and third clock signals, a read-write signal, a data input signal, first and second power supplies and a chip select signal, and generating therein a data control signal and a data control complement signal, a write circuit for producing voltage levels representative of binary information provided by the data input signal on an output node, the write circuit including a push-pull driver circuit having a pull-up fieldeffect transistor and a pull-down field-effect transistor, the improvement comprising: a first discharge circuit connected to the gate of the pull-up field-effect transistor for producing a logical exclusive OR function of the data control signal and the data input signal; a second discharge circuit connected to the gate of the pulldown field-effect transistor for producing a logical exclusive NOR function of the data control signal and the data input signal, and; a data input inverter connected to the first and second discharge circuits for providing a data input complement signal thereto.
Claim 2
Dependent Claim
168 words
In a monolithic dynamic random access memory connected to first, second and third clock signals, a read-write signal, a data input signal, first and second power supplies and a chip select signal, and generating therein a data control signal and a data control complement signal, a write circuit for producing voltage levels representative of binary information provided by the data input signal on an output node, the write circuit including a push-pull driver circuit having a pull-up fieldeffect transistor and a pull-down field-effect transistor, the improvement comprising: a first discharge circuit connected to the gate of the pull-up field-effect transistor for producing a logical exclusive OR function of the data control signal and the data input signal; a second discharge circuit connected to the gate of the pulldown field-effect transistor for producing a logical exclusive NOR function of the data control signal and the data input signal, and; a data input inverter connected to the first and second discharge circuits for providing a data input complement signal thereto.
Claim 3
Dependent Claim
84 words
The write circuit of claim 1 wherein the pull-up field-effect transistor has its drain connected to the third clock signal and its source connected to a first node, and the pull-down field-effect transistor has its drain connected to the first node and its source connected to the second power supply, and the transmission gate is a first field-effect tranSistor having its source connected to the output node and its gate connected to the third clock signal and its drain connected to the first node.
Claim 4
Dependent Claim
212 words
The write circuit of claim 1 wherein the first discharge circuit comprises second, third, fourth, fifth and sixth field-effect transistors, the second field-effect transistor having its drain connected to the gate of the pull-up field-effect transistor and its gate connected to the data control signal and its source connected to a second node, the third field-effect transistor having its drain connected to the second node and its gate connected to the data input complement signal and its source connected to a third node, the fourth field-effect transistor having its drain connected to the third node and its gate connected to the third clock signal and its source connected to the second power supply, the fifth field-effect transistor having its drain connected to the gate of the pull-up field-effect transistor and its gate connected to the data control complement signal and its source connected to a fourth node, the sixth field-effect transistor having its drain connected to the fourth node and its gate connected to the data input signal and its source connected to the second power supply, and a seventh field-effect transistor has its drain connected to the first power supply and its gate connected to the first clock signal and its source connected to the gate of the pull-up field-effect transistor.
Claim 5
Dependent Claim
212 words
The write circuit of claim 1 wherein the second discharge circuit comprises eighth, ninth, tenth, eleventh and twelfth field-effect transistors, the eighth field-effect transistor having its drain connected to the gate of the pull-down field-effect transistor and its gate connected to the data control complement signal and its source connected to a fifth node, the ninth field-effect transistor having its drain connected to the fifth node and its gate connected to the data input complement signal and its source connected to a sixth node, the tenth field-effect transistor having its drain connected to the sixth node and its gate connected to the third clock signal and its source connected to the second power supply, the eleventh field-effect transistor having its drain connected to the gate of the pull-down field-effect transistor and its gate connected to the data control signal and its source connected to a seventh node, the twelfth field-effect transistor having its drain connected to the seventh node and its gate connected to the data input signal and its source connected to the second power supply, and a thirteenth field-effect transistor has its drain connected to the first power supply and its gate connected to the first clock signal and its source connected to the gate of the pull-down field-effect transistor.
Claim 6
Dependent Claim
78 words
The write circuit of claim 1 wherein the data input inverter comprises 14th and 15th field-effect transistors, the 14th field-effect transistor having its drain connected to the first power supply and its gate connected to the first clock signal and its source connected to an eighth node, and the 15th field-effect transistor having its drain connected to the eighth node and its gate connected to the data input signal and its source connected to the second power supply.
Claim 7
Dependent Claim
84 words
In a monolithic dynamic random access memory, a decode gate circuit connected to first and second power supplies, a clock signal, and comprising a precharge device, at least one switch device and an output node, the improvement comprising an enhancement capacitor having its gate electrode connected to a boosting signal and its semiconductor material electrode connected to the output node, wherein the voltage on the output node is boosted by a pulse of the boosting signal if none of the switch devices are conducting.
Claim 8
Dependent Claim
84 words
In a monolithic dynamic random access memory, a decode gate circuit connected to first and second power supplies, a clock signal, and comprising a precharge device, at least one switch device and an output node, the improvement comprising an enhancement capacitor having its gate electrode connected to a boosting signal and its semiconductor material electrode connected to the output node, wherein the voltage on the output node is boosted by a pulse of the boosting signal if none of the switch devices are conducting.
Claim 9
Dependent Claim
14 words
The decode gate of claim 6 wherein the boosting signal is a clock signal.
Claim 10
Dependent Claim
64 words
The decode gate of claim 6 wherein the precharge device is a field-effect transistor having its drain connected to the firSt power supply and its gate connected to the clock signal and its source connected to the output node, and each switch device is a field-effect transistor having its drain connected to the output node and its source connected to the second power supply.
References Cited (Backward Citations)
US3747072A
Cited
US3795898A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-24 | 1978-08-26 | 1979-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-24 | 1982-08-26 | 1983-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-24 | 1986-08-26 | 1987-02-25 | $7700.00 | Window Closed / Lapsed |