Random access read/write semiconductor memory

Claim 2

A memory comprising: a pluralitY of memory cells formed on a substrate using integrated circuit techniques, each of said cells having first, second, third and fourth MOS devices and first and second charge pump devices, said MOS devices having first and second regions and an insulated gate, said charge pump devices having at least one first region and an insulated gate-like region, said first regions of said first and second MOS devices being coupled together and to a first power supply terminal, said first region of said first charge pump device being coupled to said second region of said first MOS device and to said gate of said second MOS device, said first region of said second charge pump device being coupled to said second region of said second MOS device and to said gate of said first MOS device, said first region of said third MOS device being coupled to said second region of said first MOS device, said first region of said fourth MOS device being coupled to said second region of said second MOS device, said second regions of said third and fourth MOS devices being coupled to first and second lines adapted to be precharged to a first voltage, said gates of said third and fourth MOS devices being coupled to an address line, said substrate being adapted for coupling to a second voltage, said gate-like region of said charge pump devices being coupled to an AC voltage input terminal; an AC voltage generating means, said generating means being coupled to said AC voltage input terminal and being a means for generating an AC voltage having a frequency of at least 100 KHz, said AC generating means further being a means for generating an AC voltage having a peak to peak amptitude at least exceeding said second voltage at one extreme and exceeding said first voltage by at least the threshold voltage of said MOS devices at the other extreme.

Claim 3

In a semiconductor memory: a plurality of memory cells arranged in rows and columns, each of said cells having first, second, third and fourth MOS devices having first and second regions and an insulated gate, said first regions of said first and second MOS devices being coupled to a power supply terminal, said second region of said first MOS devices being coupled to said first region of said third MOS device, and to said gate of said second MOS device, said second region of said second MOS device being coupled to said first region of said fourth MOS device and to said gate of said first MOS device, all of said second regions of said third MOS devices within each column of cells being coupled to a first column cell line for that column, all of said second regions of said fourth MOS devices within each column of cells being coupled to a second column cell line for that column thereby providing a pair of column cell lines for each column, all of said gates of said third and fourth MOS devices within each row of cells being coupled to a row address line for that row; sense amplifiers coupled to each pair of column cell lines, each of said sense amplifiers having fifth, sixth and seventh MOS devices, each having first and second regions and an insulated gate, said first region of said fifth MOS device being coupled to said first column cell line for a respective pair and to said gate of said sixth MOS device, said first region of said sixth MOS device being coupled to said second column cell line of said respective pair, and to said gate of said fifth MOS device, said second regions of said fifth and sixth MOS devices being coupled to said first region of said seventh MOS device, said second region of said seventh MOS device being coupled to a second power supply terminal, said gate of said seventh MOS device being coupled to a decoded column address line.

Claim 4

In a semiconductor memory: a plurality of memory cells arranged in rows and columns, each of said cells having first, second, third and fourth MOS devices having first and second regions and an insulated gate, said first regions of said first and second MOS devices being coupled to a power supply terminal, said second region of said first MOS devices being coupled to said first region of said third MOS device, and to said gate of said second MOS device, said second region of said second MOS device being coupled to said first region of said fourth MOS device and to said gate of said first MOS device, all of said second regions of said third MOS devices within each column of cells being coupled to a first column cell line for that column, all of said second regions of said fourth MOS devices within each column of cells being coupled to a second column cell line for that column thereby providing a pair of column cell lines for each column, all of said gates of said third and fourth MOS devices within each row of cells being coupled to a row address line for that row; sense amplifiers coupled to each pair of column cell lines, each of said sense amplifiers having fifth, sixth and seventh MOS devices, each having first and second regions and an insulated gate, said first region of said fifth MOS device being coupled to said first column cell line for a respective pair and to said gate of said sixth MOS device, said first region of said sixth MOS device being coupled to said second column cell line of said respective pair, and to said gate of said fifth MOS device, said second regions of said fifth and sixth MOS devices being coupled to said first region of said seventh MOS device, said second region of said seventh MOS device being coupled to a second power supply terminal, said gate of said seventh MOS device being coupled to a decoded column address line.

Claim 5

The memory of claim 2 further comprised of a means for precharging each column cell line and the line coupled to said second regions of said fifth and sixth MOS devices to a predetermined voltage.

Claim 6

The Memory of claim 2 further comprised of a means for coupling the state of each of said pair of column cell lines to a pair of output lines responsive to a signal on the respective decoded column address line.

Claim 7

In an MOS semiconductor memory having a plurality of memory cells arranged in rows and columns with each cell in each column being coupleable to a pair of column cell lines for that column to cause a differential voltage between the first and second cell lines in the pair dependent on the state of the cell, a sense amplifier for pairs of column cell lines comprising first, second and third MOS devices each having first and second regions and an insulated gate, said first region of said first MOS device being coupled to said first column cell line in a pair of lines and to said gate of said second MOS device, said first region of said second MOS device coupled to said second column cell line in the respective pair of lines and to said gate of said first MOS device, said second regions of said first and second MOS devices being coupled to said first region of said third MOS device, said third MOS device having its said second region coupled to a power supply terminal and its said gate coupled to a decoded column address line.

Claim 8

In an MOS semiconductor memory having a plurality of memory cells arranged in rows and columns with each cell in each column being coupleable to a pair of column cell lines for that column to cause a differential voltage between the first and second cell lines in the pair dependent on the state of the cell, a sense amplifier for pairs of column cell lines comprising first, second and third MOS devices each having first and second regions and an insulated gate, said first region of said first MOS device being coupled to said first column cell line in a pair of lines and to said gate of said second MOS device, said first region of said second MOS device coupled to said second column cell line in the respective pair of lines and to said gate of said first MOS device, said second regions of said first and second MOS devices being coupled to said first region of said third MOS device, said third MOS device having its said second region coupled to a power supply terminal and its said gate coupled to a decoded column address line.

Claim 9

The sense amplifiers of claim 5 further comprised of means for coupling the output of each sense amplifier to first and second output lines comprising fourth, fifth and sixth MOS devices, each having first and second regions and an insulated gate, said fourth MOS device having its said first region coupled to said second regions of said fifth and sixth MOS devices, its said gate coupled to a decoded column address line and its said second region coupled to a power supply terminal, said fifth MOS device having its said first region coupled to said first output line and its gate coupled to said first column cell line of a pair of column cell lines, and said sixth MOS device having its said first region coupled to said second output line and its gate coupled to said second column cell line of a respective pair of column cell lines.

Claim 10

The MOS semiconductor memory of claim 5 further comprised of means for precharging said column cell lines to a predetermined voltage.

Claim 11

In an MOS semiconductor memory, an input buffer comprising first, second, third and fourth MOS devices, each having first and second regions and an insulated gate, said first and second MOS devices having their first regions coupled to a power supply terminal, their said second regions coupled to said second regions of said third and fourth MOS devices, respectively, and to said gates of said second and first MOS devices respectively, said third and fourth MOS devices having their said second regions coupled to a first reference terminal and their said gates coupled to a second reference terminal, thereby defining a flip-flop means operative upon the simultaneous occurrance of reference signals on said first and second input terminals, said input buffer being further comprised of a means responsive to an input to determine the state of said flip-flop means and means for coupling the state of the flip-flop means to at least one buffer output connection.

Claim 12

In an MOS semiconductor memory, an input buffer comprising first, second, third and fourth MOS devices, each having first and second regions and an insulated gate, said first and second MOS devices having their first regions coupled to a power supply terminal, their said second regions coupled to said second regions of said third and fourth MOS devices, respectively, and to said gates of said second and first MOS devices respectively, said third and fourth MOS devices having their said second regions coupled to a first reference terminal and their said gates coupled to a second reference terminal, thereby defining a flip-flop means operative upon the simultaneous occurrance of reference signals on said first and second input terminals, said input buffer being further comprised of a means responsive to an input to determine the state of said flip-flop means and means for coupling the state of the flip-flop means to at least one buffer output connection.

Claim 13

The buffer of claim 8 wherein the state of said flip-flop means is initially determined by a capacitance between said gate of said first MOS device and said power supply terminal unless said flip-flop means is driven to the opposite state by said means responsive to an input.

Claim 14

The buffer of claim 8 wherein said means for coupling the state of the flip-flop means to at least one buffer output connection is a means for coupling the logic state of the flip-flop means and the inverse thereof to first and second buffer output connections, respectively.

Claim 15

The buffer of claim 8 wherein said first and second reference terminals are timing signal terminals.

Claim 16

The buffer of claim 8 wherein said first reference terminal is a timing signal terminal and said second reference terminal is a second power supply terminal, said gates of said third and fourth MOS devices being coupled to said second power supply terminal through a fifth MOS device having first and second regions and an insulated gate, said first region of said fifth MOS device being coupled to said gates of said third and fourth MOS devices, said gate and said second region of said fifth MOS device being coupled to said second power supply terminal, the capacitance between said gates and said second regions of said third and fourth MOS devices being substantially greater than the minimum value obtainable for such devices.

Claim 17

In an MOS semiconductor memory, using MOS devices which are conductive between first and second regions responsive to a gate voltage applied thereto, a plurality of decoders and a power save circuit: each of said decoders having first and second MOS devices and having a means for charging a decoder line to a first predetermined voltage, said decoders each having a means for receiving address signals and changing the voltage on its said decoder line to a second predetermined voltage upon the occurrance of any address signals except a specific combination of address signals, each of said decoder lines being coupled to said gate of said first MOS device, said second region of said first MOS device being coupled to said first region of said second MOS device, said second region of said second MOS device being coupled to a first power supply voltage approximately equal to said second predetermined voltage, said gate of said second MOS device being coupled to a first timing signal; said power save circuit having third and fourth MOS devices, said third MOS device having its first region coupled to a second timing signal, its gate coupled to said second region of said fourth MOS device, and its second region coupled to said first region of said first MOS devices in each decoder, said third MOS device further having a substantial capacitance coupled between its gate and its second region, said gate and said first region of said foruth MOS device being coupled to a second power supply voltage.

Claim 18

In an MOS semiconductor memory, using MOS devices which are conductive between first and second regions responsive to a gate voltage applied thereto, a plurality of decoders and a power save circuit: each of said decoders having first and second MOS devices and having a means for charging a decoder line to a first predetermined voltage, said decoders each having a means for receiving address signals and changing the voltage on its said decoder line to a second predetermined voltage upon the occurrance of any address signals except a specific combination of address signals, each of said decoder lines being coupled to said gate of said first MOS device, said second region of said first MOS device being coupled to said first region of said second MOS device, said second region of said second MOS device being coupled to a first power supply voltage approximately equal to said second predetermined voltage, said gate of said second MOS device being coupled to a first timing signal; said power save circuit having third and fourth MOS devices, said third MOS device having its first region coupled to a second timing signal, its gate coupled to said second region of said fourth MOS device, and its second region coupled to said first region of said first MOS devices in each decoder, said third MOS device further having a substantial capacitance coupled between its gate and its second region, said gate and said first region of said foruth MOS device being coupled to a second power supply voltage.

Claim 19

The apparatus of claim 13 further comprised of a generating means for generating said first timing signal, said generating means having a means for charging a line coupled to said gates of said second MOS devices to a third reference voltage, and a decoding means for changing the voltage of said line to a fourth reference voltage, said last named decoding means being a means for decoding at least one bit, and the inverse thereof, of an address signal.

Claim 20

The apparatus of claim 14 further comprised of a means for forcing said first timing signal from a voltage near said third reference voltage toward said fourth reference voltage responsive to the initial change of said timing signal toward said fourth reference voltage.

Claim 21

The apparatus of claim 14 wherein said first and third reference voltages are the same voltage and said second and fourth reference voltages are the same voltages.

Claim 22

The apparatus of claim 13 wherein each of said first MOS devices have a substantially enhanced capacitance between its gate and its second region.

Claim 23

The apparatus of claim 17 further comprised of fifth and sixth and a plurality of seventh MOS devices, said fifth MOS device having its said gate and said first region coupled to said second power supply terminal, said sixth MOS device having its said gate coupled to said second power supply terminal, its said first region coupled to said second region of said fifth MOS device, and its said second region coupled to said first power supply terminal.

Claim 24

In an MOS memory: a plurality of MOS memory cell means arranged in rows and columns, each of said memory cell means having first and second logic states; charge pumping means for maintaining the logic states of said memory cell means; row coupling means for coupling the state of each meMory cell means in a row to a respective pair of column cell lines whereby each of said pair of column cell lines may be encouraged to assume first and second opposite logic states indicative of the state of said memory cell means in said row, said row coupling means being responsive to decoded row addresses; sense amplifier means responsive to decoded column addresses, said sense amplifier means being a means for detecting a differential voltage on a pair of column cell lines and driving said column cell lines to the full logic levels of the state indicated by said differential voltage; means for coupling the logic states of the column cell lines to a pair of output lines; and means for precharging said pair of column cell lines to a predetermined voltage.

Claim 25

In an MOS memory: a plurality of MOS memory cell means arranged in rows and columns, each of said memory cell means having first and second logic states; charge pumping means for maintaining the logic states of said memory cell means; row coupling means for coupling the state of each meMory cell means in a row to a respective pair of column cell lines whereby each of said pair of column cell lines may be encouraged to assume first and second opposite logic states indicative of the state of said memory cell means in said row, said row coupling means being responsive to decoded row addresses; sense amplifier means responsive to decoded column addresses, said sense amplifier means being a means for detecting a differential voltage on a pair of column cell lines and driving said column cell lines to the full logic levels of the state indicated by said differential voltage; means for coupling the logic states of the column cell lines to a pair of output lines; and means for precharging said pair of column cell lines to a predetermined voltage.

Claim 26

In the memory of claim 19, means having substantial impedance and coupled to said predetermined voltage for encouraging each column cell line in each of said pairs of column cell lines to said predetermined voltage.

Claim 27

The memory of claim 19, further comprised of: buffer means coupled to a plurality of inputs for receiving a plurality of coded address inputs and providing as outputs each said address input and the inverse thereof upon the occurrance of a first timing signal; row address decoding means coupled to said buffer means for decoding row addresses upon the occurrance of said first timing signal and for providing to said row coupling means decoded row address signals upon the occurrance of a second timing signal; timing means coupled to said first timing signal for providing as an output a second timing signal delayed in time with respect to the occurrance of said first timing signal; and, column address decoding means coupled to said buffer means for decoding column addresses upon the occurrance of said first timing and for providing decoded column addresses to said sense amplifiers upon the occurrance of said second timing signal.

Claim 28

The memory of claim 21 wherein said buffer means are clocked flip-flop means.

Claim 29

The memory means of claim 21 wherein said timing means is coupled to at least one buffer means and includes a means for decoding one of said coded address inputs and the inverse thereof, said means for decoding one of said coded address inputs being slower in operation than said row address and said column address decoding means.

Claim 30

The memory of claim 21 further comprised of a data input means responsive to a data input signal and said first timing signal to provide said data input signal and the inverse thereof, and a read/write generator means coupled to said second timing signal, said column address decoders and each said pair of column cell lines, said read/write generator means being a means for receiving a read/write command and driving the addressed pair of column cell lines to the logic states commanded by said data input signal upon the occurrance of said second timing signal.

Claim 31

The memory of claim 24 wherein said data input means is a clocked flip-flop means.