Memory address selction apparatus including isolation circuits

Claim 2

A MOS buffer circuit connected between an input terminal and first and second output terminals, said circuit comprising: input gating means connected to said input terminal for receiving a low level input signal; output driver means coupled to said first and second output terminals and to said input gating means; and, circuit means coupled to said input gating means and to said output driver means, said circuit means including first means for applying a first timing signal to initially condition said input gating means for sampling and storing a signal representative of thE state of said input signal, said circuit means being operative to condition said output driver means so as to apply high level voltage signals of a first predetermined state to said pair of output terminals for the duration of said first timing signal, said circuit means further including second means for applying a second timing signal to said gating means, said gating means being responsive to said second timing signal to condition said output driver means in accordance with said stored signal and said input signal for enabling said driver means for switching a predetermined one of said output terminals from said first predetermined state to a second predetermined state and said circuit means including third means for applying a third timing signal to said driver means, said driver means being operative in response to said third timing signal to switch said predetermined one of said output terminals to said second predetermined state to provide a pair of complementary high level signals.

Claim 3

A buffer circuit for use in a semiconductor memory system connected between an input terminal and first and second output terminals, said circuit comprising: input gating means connected to said input terminal for receiving a low level binary signal, said gating means including first field effect transistor means and second field effect transistor means, each of said transistor means being connected to receive said low level signal and said gating means including means coupled to said first and second transistor means for receiving a predetermined clocking signal; output driver means including: a first pair of series connected field effect transistor switching means connected to said first output terminal; first capacitor means connected between an input of one of said transistor switching means and said first output terminal; a second pair of series connected field effect transistor switching means connected to said second output terminal; second capacitor means connected between the input of a corresponding one of said transistor switching means and said second output terminal; circuit means connected to said inputs of said first and second pairs of switching means and to said first and second field effect transistor means, said circuit means being responsive to a first clocking signal voltage during a first interval to charge conditionally the capacitance associated with said second field effect transistor means to store a signal in accordance with the state of said low level input signal and to charge said first and second capacitor means to a predetermined voltage, said pairs of transistor means being conditioned by said predetermined voltage to switch into conduction to force said first and second output terminals to a first voltage level; and, said means of said gating means being responsive to said predetermined clocking signal to condition one of said first and second field effect transistor means to switch into conduction in accordance with said signal stored by said capacitance and low level signal discharging one of said first and second capacitor means to a second predetermined voltage, one of said transistor means in each pair being conditioned by said second predetermined voltage to switch to a nonconductive state, and a predetermined one of said transistor means of said first and second pairs in a conductive state being operative in response to a second clocking signal to switch said one of said output terminals from said first voltage level to said second voltage level.

Claim 4

A buffer circuit for use in a semiconductor memory system connected between an input terminal and first and second output terminals, said circuit comprising: input gating means connected to said input terminal for receiving a low level binary signal, said gating means including first field effect transistor means and second field effect transistor means, each of said transistor means being connected to receive said low level signal and said gating means including means coupled to said first and second transistor means for receiving a predetermined clocking signal; output driver means including: a first pair of series connected field effect transistor switching means connected to said first output terminal; first capacitor means connected between an input of one of said transistor switching means and said first output terminal; a second pair of series connected field effect transistor switching means connected to said second output terminal; second capacitor means connected between the input of a corresponding one of said transistor switching means and said second output terminal; circuit means connected to said inputs of said first and second pairs of switching means and to said first and second field effect transistor means, said circuit means being responsive to a first clocking signal voltage during a first interval to charge conditionally the capacitance associated with said second field effect transistor means to store a signal in accordance with the state of said low level input signal and to charge said first and second capacitor means to a predetermined voltage, said pairs of transistor means being conditioned by said predetermined voltage to switch into conduction to force said first and second output terminals to a first voltage level; and, said means of said gating means being responsive to said predetermined clocking signal to condition one of said first and second field effect transistor means to switch into conduction in accordance with said signal stored by said capacitance and low level signal discharging one of said first and second capacitor means to a second predetermined voltage, one of said transistor means in each pair being conditioned by said second predetermined voltage to switch to a nonconductive state, and a predetermined one of said transistor means of said first and second pairs in a conductive state being operative in response to a second clocking signal to switch said one of said output terminals from said first voltage level to said second voltage level.

Claim 5

In a MOS memory system comprising a plurality of MOS memory cells arranged in an array so as to connect in rows and columns, a plurality of X and Y selection lines, each coupled to different rows and columns of groups of said plurality of memory cells, a plurality of X and Y decoder circuits, each having a plurality of input terminals and an output terminal, each said output terminal of each of said X decoder circuits being coupled to a difFerent one of said X selection lines and each said output terminal of said Y decoder circuits being coupled to a corresponding one of said Y selection lines, said system further including: a plurality of address input lines, said lines each being coupled to receive a different one of a plurality of low level digital address signals representative of a corresponding number of address information digits applied to said address input lines; and a corresponding number of input buffer circuits for generating pairs of complementary address signals, each of said buffer circuits having an input terminal being coupled to a different one of said address lines and a pair of output terminals coupled to at least one input terminal of a different one of said plurality of X and Y decoder circuits and each of said buffer circuits including: an input gating means coupled to said input terminal for receiving one low level signal; output driver means coupled to said pair of output terminals; and, circuit means coupled to said input buffer circuits for applying a predetermined sequence of timing signals thereto, said circuit means including first means for applying a first timing signal to said input gating means and to said output driver means, said input gating means of each of said buffer circuits being operative in response to said first signal to store a voltage representative of the state of said low level address signal applied to each said input terminal and each said output driver means being operative in response to said first timing signal to apply high level voltage signals of a first predetermined state to said pair of output terminals for the duration of said first timing signal, said circuit means further including second means for applying a second timing signal to said gating means of each of said buffer circuits, each said input gating means being responsive to said second timing signal to condition selectively said output driver means associated therewith in accordance with said voltage to enable one of said output terminals to be switched from said first predetermined state to a second predetermined state and said circuit means including third means for applying a third timing signal to said driver means of each of said buffer circuits, each said driver means being responsive to said third timing signal from said circuit means to switch said one of said output terminals to said second predetermined state to provide a different one of said pairs of complementary high level address signals.

Claim 6

In a MOS memory system comprising a plurality of MOS memory cells arranged in an array so as to connect in rows and columns, a plurality of X and Y selection lines, each coupled to different rows and columns of groups of said plurality of memory cells, a plurality of X and Y decoder circuits, each having a plurality of input terminals and an output terminal, each said output terminal of each of said X decoder circuits being coupled to a difFerent one of said X selection lines and each said output terminal of said Y decoder circuits being coupled to a corresponding one of said Y selection lines, said system further including: a plurality of address input lines, said lines each being coupled to receive a different one of a plurality of low level digital address signals representative of a corresponding number of address information digits applied to said address input lines; and a corresponding number of input buffer circuits for generating pairs of complementary address signals, each of said buffer circuits having an input terminal being coupled to a different one of said address lines and a pair of output terminals coupled to at least one input terminal of a different one of said plurality of X and Y decoder circuits and each of said buffer circuits including: an input gating means coupled to said input terminal for receiving one low level signal; output driver means coupled to said pair of output terminals; and, circuit means coupled to said input buffer circuits for applying a predetermined sequence of timing signals thereto, said circuit means including first means for applying a first timing signal to said input gating means and to said output driver means, said input gating means of each of said buffer circuits being operative in response to said first signal to store a voltage representative of the state of said low level address signal applied to each said input terminal and each said output driver means being operative in response to said first timing signal to apply high level voltage signals of a first predetermined state to said pair of output terminals for the duration of said first timing signal, said circuit means further including second means for applying a second timing signal to said gating means of each of said buffer circuits, each said input gating means being responsive to said second timing signal to condition selectively said output driver means associated therewith in accordance with said voltage to enable one of said output terminals to be switched from said first predetermined state to a second predetermined state and said circuit means including third means for applying a third timing signal to said driver means of each of said buffer circuits, each said driver means being responsive to said third timing signal from said circuit means to switch said one of said output terminals to said second predetermined state to provide a different one of said pairs of complementary high level address signals.

Claim 7

In the system of claim 3 wherein said system further includes: circuit means being connected to apply said first timing signal to each of said plurality of X and Y decoder circuits; each of said decoder circuits being conditioned by said first predetermined state of said buffer circuit output terminals applied to said decoder circuit input terminals to respond to said first timing signal by charging each of said X and Y selection lines to said second predetermined state; and, each of said decoder circuits being responsive to a switching of one of said input terminals from said first predetermined state to said second predetermined state to switch a corresponding one of said selection lines from said second predetermined state to said first predetermined state whereby only the X and Y selection line designated by said address signals remains in said second predetermined state.

Claim 8

In the system of claim 4 wherein the voltage levels corresponding to said first predetermined state and said second predetermined state are selected to be representative of a binary ZERO and a binary ONE respectively to enhance the response time of said X and Y decoder circuits by discharging all of said decoder circuits except the X and Y decoder circuits of said X and Y designated by said address signals.

Claim 9

In the system of claim 3 wherein said circuit means further includes means for applying to said second and third means respectIvely said second and third timing signals timed to overlap one another.

Claim 10

In the system of claim 3 wherein said circuit means includes timing means having an input terminal coupled to said first means and first and second output terminals coupled to said second and third means respectively, said timing means comprising: transistor inverter switching means having gate, source and drain electrodes, said gate electrode being connected to said input terminal to receive said first timing signal, said source electrode being connected to a first reference voltage and said drain electrode being connected to a second reference voltage and to said first output terminal; first transistor output driver means having gate, source and drain electrodes, said gate electrode being connected to said first output terminal, said source electrode being connected to said second output terminal and said drain electrode being connected to said second reference voltage; second transistor output driver means having gate, source and drain electrodes, said gate electrode being connected to said input terminal, said source electrode being connected to said first reference voltage and said drain electrode being connected to said second output terminal; and, capacitor means connected between said gate electrode of said first transistor driver means and a reference potential so as to delay by a predetermined amount the switching of said first transistor output driver means in response to said first timing signal to produce said second and third timing signals at said first and second terminals respectively inverted with respect to said first timing signal and overlapping in time to one another by said predetermined amount.

Claim 11

In the system of claim 7 wherein said transistor switching means, said first transistor output driver means and said second transistor out-put driver means each include P channel field effect transistors and said capacitor means includes a discrete capacitor.

Claim 12

In the memory system of claim 3 wherein each said input gating means has an input terminal and a plurality of output terminals and includes: a clocked transistor current source being connected to receive said second timing signal; a first transistor switching device having gate, source and drain electrodes, said gate electrode being connected to said input terminal, said source electrode being connected to said clocked current source and said drain electrode being connected to said first means and to said output driver means; a second transistor switching device having gate, source and drain electrodes, said gate and drain electrodes being connected to said first means; capacitance means connected between a reference potential and said gate electrode of said second switching device; transistor switching means connected between said gate electrode of said second switching device and said input terminal; said circuit means including transistor means connected to said first means, said transistor means being operative in response to said first timing signal to charge said capacitance means during a first interval to a predetermined state, said transistor switching means being arranged to discharge selectively said capacitance means in accordance with the state of said input address signal thereby resulting in the storage of a voltage representative of said state on said capacitance means; and, said first and second transistor switching devices being selectively switched into conduction by said address signal and said stored signal respectively to switch into conduction upon being conditioned by said clocked current source in response to said second clocking signal, said first and second transistor switching device conditioning said output driver means to enable one of said buffer output terminals to be switched to said second predetermined state.

Claim 13

In the memory system of claim 9 wherein the gain of said transistor switching means selected to be is substantiaLly greater than the gain of said transistor means.

Claim 14

In the memory system of claim 9 wherein each of said output driver means includes: first and second driver switching means, each of said driver switching means including: a first transistor switching device, said device having gate and source and drain electrodes, said source electrode being connected to said one of said output terminals and said drain electrode being connected to said circuit means; capacitor means connected between said gate and source electrodes of said first switching device; a second switching device, said device having gate and source and drain electrodes, said drain electrode being connected to said one of said output terminals, said source electrode being connected to a reference voltage; capacitance means connected to said gate electrode of said second switching device; and wherein each said buffer circuit includes means interconnecting said gate electrode of said first switching device of each of said first driver switching means to a predetermined one of said input gating output terminals in common with said gate electrode of said second switching device of said second driver switching means, a selected one of said first and second switching devices of said first and second switching means being switched from a conductive state to a nonconductive state in accordance with said state of said address signal to the conductive one of said first switching devices being conditioned by a predetermined voltage level of said third timing signal at the termination of said first timing interval to switch one of said output terminals to said second predetermined state.

Claim 15

In the system of claim 9 wherein said clocked current source includes: a switching device having gate, source and drain electrodes, said gate electrode being connected to receive said second timing signal, said source electrode being connected to a reference voltage and said drain electrode being connected to said source electrodes of said first and second switching devices, said device being conditioned to conduct in response to said second timing signal to supply current to said first and second switching devices.

Claim 16

In the system of claim 9 wherein said switching means includes: a switching device having gate, source and drain electrodes, said gate electrode being connected to said input terminal, said source electrode being connected to said reference voltage and said drain electrode being connected to said gate electrode of said second switching device; and, said switching device being conditioned to discharge conditionally said capacitance means to said reference voltage in accordance with the state of said address signal applied to said input terminal during an interval defined by said first timing signal.

Claim 17

In the system of claim 9 wherein said first and second switching devices are insulated gate field effect transistors.

Claim 18

In the system of claim 14 wherein said field effect transistors are P channel enhancement type transistors.

Claim 19

In the system of claim 12 wherein said switching device is an insulated gate field effect transistor.

Claim 20

In the system of claim 15 wherein said field effect transistors are P channel enhancement type transistors.

Claim 21

In the system of claim 11 wherein said capacitor means of each of said driver switching means is a discrete capacitor whose value is selected relative to said capacitance means of the other of said driver switching means to condition the conductive one of said first transistor switching devices of said driver means to produce an output signal at said output terminal which approximates in magnitude the voltage of said third timing signal.

Claim 22

In the system of claim 11 wherein said capacitance means of said second switching device of each of said driver switching means includes the intrinsic capacitance of said gate electrode of second transistor switching device.

Claim 23

A MOS buffer circuit connected between an iNput terminal and a pair of output terminals for translating a low level input signal applied to said input terminal into a pair of complementary high level signals applied to said output terminals, said buffer circuit comprising: an input logic means including: a clocked transistor current source connected to receive a first predetermined clocking signal; a first active switching device having a control electrode, a pair output electrodes, said control electrode being connected to said input terminal; a second active switching device having a control electrode and pair of output electrodes, one of said output electrodes of each of said first and second active devices being connected in common to said clocked current source; node capacitor means connected between a reference voltage and said control electrode of said second active switching device; and, transistor current source means connected to said input terminal and to said control electrode of said second switching device; an output driver means including: first and second driver switching means, each of said driver switching means including; first and second series connected switching devices, each device having a control electrode and a pair of output electrodes, and capacitor means, said capacitor means being connected between said control electrode and one of said output electrodes of said first device, the other output electrode of said first device of each driver switching means being connected to receive a second predetermined clocking signal, one of said output electrodes of said each second switching device of said first and second driver switching means being connected to a different one of said output terminals in common with said one of said output electrodes of said first device, the other of said output electrodes of each said second switching device being connected to a first reference voltage, and said control electrodes of said first device of each of said driver switching means and said second device of the other of said driver switching means being connected in common to the other one of said output electrodes of a different one of said switching devices of said logic means; and, precharge circuit means being responsive to a first clocking signal to charge said capacitor means of said first and second driver switching means to a first predetermined voltage, said first and second switching devices of each of said driver means being conditioned by said predetermined voltage to switch into conduction to apply a first predetermined high level voltage to each of said output terminals during a first interval defined by said first clocking signal; said precharge circuit means including transistor means operative in response to said first clocking signal to charge said capacitor means of said second switching device of said input logic means to a second predetermined voltage and said current source being operative to discharge selectively said capacitor means from said second predetermined voltage in accordance with the state of said input signal to a voltage representative of said input signal; said first and second active switching devices of said input gating means being selectively conditioned by said low level input signal and said voltage to be switched into conduction by said clocked current source in response to said first predetermined clocking signal for discharging selectively from said first predetermined voltage one of said capacitor means of one of said driver switching means in accordance with the state of said input signal, said first predetermined voltage of the other capacitor means conditioning one of said first switching devices and one of said second switching devices to remain conductive, said one of said first switching devices in response to said second predetermined clocking signal being operative to switch one of said output terminals from said first predetermined high voltage level to a second predetermined high voltage level aT the termination of said first interval.

Claim 24

A MOS buffer circuit connected between an iNput terminal and a pair of output terminals for translating a low level input signal applied to said input terminal into a pair of complementary high level signals applied to said output terminals, said buffer circuit comprising: an input logic means including: a clocked transistor current source connected to receive a first predetermined clocking signal; a first active switching device having a control electrode, a pair output electrodes, said control electrode being connected to said input terminal; a second active switching device having a control electrode and pair of output electrodes, one of said output electrodes of each of said first and second active devices being connected in common to said clocked current source; node capacitor means connected between a reference voltage and said control electrode of said second active switching device; and, transistor current source means connected to said input terminal and to said control electrode of said second switching device; an output driver means including: first and second driver switching means, each of said driver switching means including; first and second series connected switching devices, each device having a control electrode and a pair of output electrodes, and capacitor means, said capacitor means being connected between said control electrode and one of said output electrodes of said first device, the other output electrode of said first device of each driver switching means being connected to receive a second predetermined clocking signal, one of said output electrodes of said each second switching device of said first and second driver switching means being connected to a different one of said output terminals in common with said one of said output electrodes of said first device, the other of said output electrodes of each said second switching device being connected to a first reference voltage, and said control electrodes of said first device of each of said driver switching means and said second device of the other of said driver switching means being connected in common to the other one of said output electrodes of a different one of said switching devices of said logic means; and, precharge circuit means being responsive to a first clocking signal to charge said capacitor means of said first and second driver switching means to a first predetermined voltage, said first and second switching devices of each of said driver means being conditioned by said predetermined voltage to switch into conduction to apply a first predetermined high level voltage to each of said output terminals during a first interval defined by said first clocking signal; said precharge circuit means including transistor means operative in response to said first clocking signal to charge said capacitor means of said second switching device of said input logic means to a second predetermined voltage and said current source being operative to discharge selectively said capacitor means from said second predetermined voltage in accordance with the state of said input signal to a voltage representative of said input signal; said first and second active switching devices of said input gating means being selectively conditioned by said low level input signal and said voltage to be switched into conduction by said clocked current source in response to said first predetermined clocking signal for discharging selectively from said first predetermined voltage one of said capacitor means of one of said driver switching means in accordance with the state of said input signal, said first predetermined voltage of the other capacitor means conditioning one of said first switching devices and one of said second switching devices to remain conductive, said one of said first switching devices in response to said second predetermined clocking signal being operative to switch one of said output terminals from said first predetermined high voltage level to a second predetermined high voltage level aT the termination of said first interval.

Claim 25

The buffer circuit of claim 20 wherein said transistor current source means includes: a field effect transistor having a control electrode and first and second output electrodes, said gate electrode being connected to said input terminal one of said output electrodes being connected to said first reference voltage and the other of said output electrodes being connected to said control electrode of said second switching device; and wherein said transistor means of said precharge circuit means includes: a field effect transistor having a control electrode and first and second output electrodes, said control electrode being connected to receive said first clocking signal, one of said output electrodes being connected to a second reference voltage and the other of said output electrodes being connected to said control electrode of said input gating second active-switching device; and, said field effect transistor of said current source means being selected to have a gain substantially greater than the gain of said field effect transistor of said precharge circuit to discharge selectively said capacitor means to said first reference voltage in accordance with the state of said low level input signal during the time interval of said first clocking signal.

Claim 26

The buffer circuit of claim 20 further including: timing means having an input terminal connected to receive said first clocking signal and first and second output terminals, said timing means being responsive to said first clocking signal to generate said first predetermined clocking signals at said first and second output terminals respectively inverted with respect to said first clocking signal, said timing means including means for delaying said second predetermined clocking signal being delayed by a predetermined amount relative to said first predetermined clocking signal to provide sufficient time for discharging said capacitor means of said driver switching means.

Claim 27

The buffer circuit of claim 20 wherein said capacitor means of each of said driver switching means includes: a discrete capacitor having a value of capacitance relative to the effective capacitance associated with said control electrode of said first switching device for retaining enough voltage for driving said control electrode so that said second predetermined high voltage level approximates the voltage level of said second predetermined clocking signal.

Claim 28

The buffer circuit of claim 20 wherein said precharge circuit transistor means includes: a first field effect transistor having a control electrode and first and second output electrodes, said control electrode being connected to receive said first clocking singal, said first output electrode being connected to a second reference voltage and said second output electrode being connected to said control electrode of said second active switching device; and, wherein said precharge circuit means further includes: second and third field effect transistors, each having a control electrode and first and second output electrodes, said control electrode being connected to receive said first clocking signal, said first output electrode being connected to said second reference voltage and said second and third transistors being connected to said output electrode of said different one of said switching devices, said first, second and third transistors being responsive to said first clocking signal to charge said capacitor means of said control electrode of said second switching device of said input gating means, said capacitor means of said first device of said first driver switching means and said capacitor means of said first device of said second driver switching means respectively.