US3747072A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated static mnos memory circuit
Assignee: Unisys Corp
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Filing: 1972-07-19
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Granted: 1973-07-17
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Expires: 1992-07-19
Abstract
Abstract A memory array employs individual variable threshold MNOS transistors as memory cells. A decoder employs a binary coded address signal to select a desired word in the memory. A decoder buffer translates the output of the decoder into the true or complement of the output signal of the buffer and places the resulting signal on the gate electrode of the variable threshold MNOS transistors constituting a given word line. A READ/WRITE contact receives a signal that determines the mode of operation of the memory. An input/output buffer at the end of each bit line in the memory array converts an input signal into an inhibit or WRITE signal in response to a control signal passed through a control section when the READ/WRITE circuit receives a signal suitable for switching the memory into the WRITE mode. If the signal on the READ/WRITE contact has switched the circuit into the READ mode, the input/output buffer serves to gate output current to exterior circuits. The control section also provides suitable substrate voltages to the memory array.
Inventors
- 👤 R Lodi
- 👤 H Wegener
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
434 words
A digital memory comprising an array of variable threshold transistor memory cells formed on a substrate and arranged in word rows and bit columns, each of said cells having gate, source, and drain electrodes; a. terminal means for receiving externally generated address, control, READ/WRITE, and inhibit signals; b. word address matrix means for actuating the gate electrodes of a single row of memory cells selected in accordance with an address signal; c. first means for applyinG bias voltages to said substrate; d. second means for applying drain voltages to the memory cells in individual bit columns; e. means to clear individual word rows, including: 1. decoder buffer means responsive to a zero level control signal for applying a zero level voltage to the gate electrodes in the row of memory cells selected by said matrix and a high level voltage to the gate electrodes of the remaining memory cells; 2. means in said first means for providing a substrate voltage equal to said high level voltage in response to said zero level control signal; f. means to write information into said array in response to a specified large control signal, including: 1. means in said decoder buffer means for applying a gate voltage equal to said high level voltage to the gate electrodes in the row of memory cells selected by said matrix and a zero level voltage to the gate electrodes of the remaining memory cells: 2. means in said first means for providing a zero level substrate voltage in response to said specified large control signal; 3. said second means being responsive to individual inhibit signals corresponding to each bit column and arranged to supply high level drain voltages to the memory cells in those bit columns receiving inhibit signals and zero level drain voltages to the memory cells in those bit columns not receiving inhibit signals; g. means to read information out of said array in response to a specified intermediate value control signal and a received READ signal, including: 1. means in said decoder buffer means for applying an intermediate level voltage to the gate electrodes in the row of memory cells selected by said matrix and a zero level voltage to the gate electrodes of the remaining memory cells: 2. means in said first means for providing a zero level substrate voltage in response to said intermediate value control signal; 3. means in said second means for providing high level drain voltages in response to said intermediate level control signal, said second means further containing means for connecting the source electrodes of the memory cells to exterior utilization apparatus.
Claim 2
Dependent Claim
434 words
A digital memory comprising an array of variable threshold transistor memory cells formed on a substrate and arranged in word rows and bit columns, each of said cells having gate, source, and drain electrodes; a. terminal means for receiving externally generated address, control, READ/WRITE, and inhibit signals; b. word address matrix means for actuating the gate electrodes of a single row of memory cells selected in accordance with an address signal; c. first means for applyinG bias voltages to said substrate; d. second means for applying drain voltages to the memory cells in individual bit columns; e. means to clear individual word rows, including: 1. decoder buffer means responsive to a zero level control signal for applying a zero level voltage to the gate electrodes in the row of memory cells selected by said matrix and a high level voltage to the gate electrodes of the remaining memory cells; 2. means in said first means for providing a substrate voltage equal to said high level voltage in response to said zero level control signal; f. means to write information into said array in response to a specified large control signal, including: 1. means in said decoder buffer means for applying a gate voltage equal to said high level voltage to the gate electrodes in the row of memory cells selected by said matrix and a zero level voltage to the gate electrodes of the remaining memory cells: 2. means in said first means for providing a zero level substrate voltage in response to said specified large control signal; 3. said second means being responsive to individual inhibit signals corresponding to each bit column and arranged to supply high level drain voltages to the memory cells in those bit columns receiving inhibit signals and zero level drain voltages to the memory cells in those bit columns not receiving inhibit signals; g. means to read information out of said array in response to a specified intermediate value control signal and a received READ signal, including: 1. means in said decoder buffer means for applying an intermediate level voltage to the gate electrodes in the row of memory cells selected by said matrix and a zero level voltage to the gate electrodes of the remaining memory cells: 2. means in said first means for providing a zero level substrate voltage in response to said intermediate value control signal; 3. means in said second means for providing high level drain voltages in response to said intermediate level control signal, said second means further containing means for connecting the source electrodes of the memory cells to exterior utilization apparatus.
Claim 3
Dependent Claim
41 words
means in said first means for providing a substrate voltage equal to said high level voltage in response to said zero level control signal; f. means to write information into said array in response to a specified large control signal, including:
Claim 4
Dependent Claim
41 words
means in said first means for providing a substrate voltage equal to said high level voltage in response to said zero level control signal; f. means to write information into said array in response to a specified large control signal, including:
Claim 5
Dependent Claim
20 words
means in said first means for providing a zero level substrate voltage in response to said specified large control signal;
Claim 6
Dependent Claim
20 words
means in said first means for providing a zero level substrate voltage in response to said specified large control signal;
Claim 7
Dependent Claim
20 words
means in said first means for providing a zero level substrate voltage in response to said intermediate value control signal;
Claim 8
Dependent Claim
20 words
means in said first means for providing a zero level substrate voltage in response to said intermediate value control signal;
Claim 9
Dependent Claim
106 words
The memory of claim 1 wherein said address signals include a plurality of binary signals coded so that a different combination is available for each row of memory cells and said matrix means includes decoder means having an individual output line corresponding to each row of memory cells, said output line being coupled to said decoder buffer means, said decoder buffer means including switching transistor means for modifying the signals in said output lines in response to said control signals, said switching transistor means being further arranged to apply the modified signals to the gate electrodes of the memory cells in the corresponding row of cells.
Claim 10
Dependent Claim
159 words
The memory of claim 2 in which said switching transistor means includes a buffer driver transistor connected in series relationship with a buffer load transistor for each row of memory cells, said buffer driver transistor having a gate electrode connected to the corresponding output line from said decoder means, the junction of said driver and load transistors being connected to the gate electrodes of a corresponding memory cell, said decoder buffer means including a buffer drive means for providing drain and load voltages to all of the driver and load transistors respectively and a gate voltage to gate electrodes on all of said load transistors, respectively, said buffer drive means being arranged to supply a low level drive voltage and high level load and gate voltages in response to a zero level control voltage and a high level drive voltage, a low level load voltage and an intermediate level gate voltage in response to a high level control voltage.
Claim 11
Dependent Claim
38 words
means in said second means for providing high level drain voltages in response to said intermediate level control signal, said second means further containing means for connecting the source electrodes of the memory cells to exterior utilization apparatus.
Claim 12
Dependent Claim
38 words
means in said second means for providing high level drain voltages in response to said intermediate level control signal, said second means further containing means for connecting the source electrodes of the memory cells to exterior utilization apparatus.
Claim 13
Dependent Claim
74 words
said second means being responsive to individual inhibit signals corresponding to each bit column and arranged to supply high level drain voltages to the memory cells in those bit columns receiving inhibit signals and zero level drain voltages to the memory cells in those bit columns not receiving inhibit signals; g. means to read information out of said array in response to a specified intermediate value control signal and a received READ signal, including:
Claim 14
Dependent Claim
74 words
said second means being responsive to individual inhibit signals corresponding to each bit column and arranged to supply high level drain voltages to the memory cells in those bit columns receiving inhibit signals and zero level drain voltages to the memory cells in those bit columns not receiving inhibit signals; g. means to read information out of said array in response to a specified intermediate value control signal and a received READ signal, including:
Claim 15
Dependent Claim
75 words
The memory of claim 3 further characterized in that said second means includes a transistor network for coupling the drain terminals of the memory Cells in the corresponding bit column to a source of high level voltage, said transistor network further including a memory driving transistor for optionally connecting the same drain terminals to ground potential in response to a high level READ/WRITE or inhibit signal or in response to a zero level control signal.
Claim 16
Dependent Claim
78 words
The memory of claim 4 wherein the means for connecting the source electrodes of the memory cells to external utilization apparatus includes individual gating transistors corresponding to each of said bit columns, said gating transistors being arranged for serial connection between the source electrodes of all memory cells in the associated bit column and the utilization apparatus, said gating transistors further being arranged to saturate only in response to a combination of high level READ/WRITE and control voltages.
Claim 17
Dependent Claim
343 words
A digital memory comprising an array of variable threshold transistor memory cells formed on a substrate and arranged in word rows and bit columns, each of said cells having gate, source and drain electrodes, word addressing means for selecting a single word row to be actuated in response to received address signals, decoder means in said addressing means, said decoder means including a plurality of output lines equal in number to the number of word rows in said memory, said decoder means including means for forming a first predetermined decoder output signal on an output line corresponding to a selected word row and second predetermined decoder output signals on the remaining output lines, means for receiving externally generated control signals, first buffer means for supplying individual gate signals to each word row in said memory, each of said gate signals corresponding to a different one of the decoder output signals, said first buffer means supplying gate signals that represent the True value of the decoder output signals when a received control signal has a predetermined high value and the Complementary value of the decoder output signals when the received control signal has a predetermined low value, substrate driving means responsive to a control signal of said low value for applying a voltage to said substrate equal in value to the gate voltages applied to non-slected word rows by the same control signal, and individual input/output buffers coupled to each bit column, said input/output buffers being constructed and arranged to apply source and drain voltages to the memory cells in the associated bit column in response to externally generated control, READ/WRITE and input/output signals, means in each of said input/output buffers for applying source and drain voltages equal to said substrate voltage when and only when said control voltage has a high value and said READ/WRITE and input/output signals have a low value, further means in each of said input/output buffer means for gating out current pulses from the associated bit line memory cells when said control and READ/WRITE signals have a high value.
Claim 18
Dependent Claim
343 words
A digital memory comprising an array of variable threshold transistor memory cells formed on a substrate and arranged in word rows and bit columns, each of said cells having gate, source and drain electrodes, word addressing means for selecting a single word row to be actuated in response to received address signals, decoder means in said addressing means, said decoder means including a plurality of output lines equal in number to the number of word rows in said memory, said decoder means including means for forming a first predetermined decoder output signal on an output line corresponding to a selected word row and second predetermined decoder output signals on the remaining output lines, means for receiving externally generated control signals, first buffer means for supplying individual gate signals to each word row in said memory, each of said gate signals corresponding to a different one of the decoder output signals, said first buffer means supplying gate signals that represent the True value of the decoder output signals when a received control signal has a predetermined high value and the Complementary value of the decoder output signals when the received control signal has a predetermined low value, substrate driving means responsive to a control signal of said low value for applying a voltage to said substrate equal in value to the gate voltages applied to non-slected word rows by the same control signal, and individual input/output buffers coupled to each bit column, said input/output buffers being constructed and arranged to apply source and drain voltages to the memory cells in the associated bit column in response to externally generated control, READ/WRITE and input/output signals, means in each of said input/output buffers for applying source and drain voltages equal to said substrate voltage when and only when said control voltage has a high value and said READ/WRITE and input/output signals have a low value, further means in each of said input/output buffer means for gating out current pulses from the associated bit line memory cells when said control and READ/WRITE signals have a high value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-16 | 1977-01-15 | 1977-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-16 | 1981-01-15 | 1981-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-16 | 1985-01-15 | 1985-07-17 | $7700.00 | Window Closed / Lapsed |