Delay circuit with field effect transistors

Claim 2

A delay circuit with field effect transistors which is based on the discharge of a first capacitive element caused by an input signal to be delayed; at least one input switching stage representing the actual delay device, said first capacitive element being effective at the output of said switching stage; a second switching stage in series with said input switching stage acting as a voltage sensing device and as an output driver of the input signal to be delayed, being coupled to said first capacitive element; a second capacitive element in the first switching stage coupling the input signal to be delayed to the previously charged first capacitive element to thus increase its precharge value; and means for the constant current discharge of said first capacitive element to at least the switching threshold of said series arranged second switching stage.

Claim 3

The delay circuit as claimed in claim 1 wherein the capacitance effective at the output of the input switching stage of said first capacitive element is formed by the parasitic gate capacitance of field effect transistors of said second stage.

Claim 4

A delay circuit with field effect transistors which is based on the discharge of a first capacitive element caused by an input signal to be delayed; at least one input switching stage representing the actual delay device, said first capacitive element being effective at the output of said switching stage; a second switching stage in series with said input switching stage acting as a voltage sensing device and as an output driver of the input signal to be delayed, being coupled to said first capacitive element; and additional charge means to additionally charge said first capacitive element to a high value from at least the switching threshold of said series arranged stage; said input switching stage being an inverter which comprises in series arrangement a driver and a load FET with an output at the joint connecting point, a second capacitive element being effective at said connecting point, the input signal to be delayed being coupled via said second capacitive element to the connecting point and to the gate electrode of the driver FET.

Claim 5

A delay circuit with field effect transistors which is based on the discharge of a first capacitive element caused by an input signal to be delayed; at least one input switching stage representing the actual delay device, said first capacitive element being effective at the output of said switching stage; a second switching stage in series with said input switching stage acting as a voltage sensing device and as an output driver of the input signal to be delayed, being coupled to said first capacitive element; and additional charge means to additionally charge said first capacitive element to a high value from at least the switching threshold of said series arranged stage; said input switching stage being an inverter which comprises in series arrangement a driver and a load FET with an output at the joint connecting point, a second capacitive element being effective at said connecting point, the input signal to be delayed being coupled via said second capacitive element to the connecting point and to the gate electrode of the driver FET.

Claim 6

The delay circuit as claimed in claim 3 wherein said first capacitance effective at the output of the input switching stage of the capacitive element is formed by the parasitic gate capacitance of the field effect transistors of the series arranged stage.

Claim 7

The delay circuit as claimed in claim 4 wherein the capacitance of said first capacitive element effective at the output of the input switching stage is smaller than that of said second capacitive coupling element.

Claim 8

The delay circuit as claimed in claim 5 wherein the charging of said first capacitive element at the output of the input inverter is effected via the associated load FET up to said high value.

Claim 9

The delay circuit as claimed in claim 6 wherein the charging of said first capacitive element effective at the output of the input inverter is provided during a clock phase provided prior to the appearance of the input signal to be delayed.

Claim 10

The delay circuit as claimed in claim 7 wherein the input inverter for charging said first capacitive element is a bootstrap stage.

Claim 11

The delay circuit as claimed in claim 8 wherein the sensing and driver circuit is a bootstrap stage.

Claim 12

The delay circuit as claimed in claim 9 wherein the driver FET is operated in the saturation region during the discharging of said first capacitive element.

Claim 13

The delay circuit as claimed in claim 10 wherein during the discharging of said first capacitive element the gate voltage of the driver FET is almost constant, being raised only slightly over the value of the threshold voltage.

Claim 14

The delay circuit as claimed in claim 11 wherein a switched path of another FET is positioned between the circuit input and the gate electrode of the driver FET with the switched path of the other FET having a transfer impedance that is higher with respect to the driver FET.

Claim 15

The delay circuit as claimed in claim 12 wherein the gate electrode of the other FET is applied to a fixed voltage corresponding to the operation voltage.

Claim 16

The delay circuit as claimed in claim 13 wherein the gate electrode of the other FET is connected to the circuit input.

Claim 17

The delay circuit as claimed in claim 14 wherein a parallel FET is provided in parallel to the gate-source path of the driver FET, said parallel FET being controllable during the charging phase via a pulse applied at its gate electrode.

Claim 18

The delay circuit as claimed in claim 15 including a voltage divider stage switchable by the input signal comprising an FET simulating the driver FET with respect to its threshold voltage, the gate voltage for the driver FET following the equation v G = V T + ΔV being derived from said voltage divider stage, ΔV being a constant.

Claim 19

The delay circuit as claimed in claim 16 wherein the voltage corresponding to the constant ΔV is derived from a further voltage divider switchable by the input signal.

Claim 20

An FET delay circuit comprising: an input stage having an input terminal for receiving an input signal to be delayed and an output terminal having a load capacitance; a first FET device in said input stage, having its drain connected to said output terminal and its source connected to a reference potential; a precharge means in said input stage, connected to said output terminal for precharging said load capacitance during a first period to a first potential; a capacitor in said input stage, connected between said input terminal and said output terminal, having a capacitance greater than said load capacitance, for forming a capacitor divider with said load capacitance, to transmit said input signal from said input terminal to said output terminal during a second period following said first period, to boost the magnitude of said input signal at said output terminal to a second potential greater than said first potential; a second FET device in said input stage, having its source-drain path connected between said input terminal and the gate of said first FET device, with the gate of said second FET device connected to said input terminal, for delaying the application of said input signal to said gate of said first FET device until a third period following said second period, to turn said first FET device on, discharging said load capacitance and reducing the magnitude of the voltage at said output terminal; a driver stage having an input terminal connected to the output terminal of said input stage and an output terminal; a third FET device in said driver stage, having its drain connected to said output terminal of said driver stage, its source connected to a reference potential, and its gate connected to said input terminal of said driver stage, for separating said load capacitance from said output terminal of said driver; a load impedance in said driver stage connected between the output terminal of said driver stage and a drain voltage; said magnitude of said voltage at said output terminal of said input stage during said second period being sufficiently high to cause said third FET device to conduct, generating a relatively low output voltage at said output terminal of said driver stage; said reduction in the magnitude of said voltage at said output terminal of said input stage during said third period causing said third FET device to stop conduction, generating a relatively high output voltage at said output terminal of said driver stage, having a fast transition due to the lack of capacitive loading thereon; whereby a delayed signal may have a fast transition time.

Claim 21

An FET delay circuit comprising: an input stage having an input terminal for receiving an input signal to be delayed and an output terminal having a load capacitance; a first FET device in said input stage, having its drain connected to said output terminal and its source connected to a reference potential; a precharge means in said input stage, connected to said output terminal for precharging said load capacitance during a first period to a first potential; a capacitor in said input stage, connected between said input terminal and said output terminal, having a capacitance greater than said load capacitance, for forming a capacitor divider with said load capacitance, to transmit said input signal from said input terminal to said output terminal during a second period following said first period, to boost the magnitude of said input signal at said output terminal to a second potential greater than said first potential; a second FET device in said input stage, having its source-drain path connected between said input terminal and the gate of said first FET device, with the gate of said second FET device connected to said input terminal, for delaying the application of said input signal to said gate of said first FET device until a third period following said second period, to turn said first FET device on, discharging said load capacitance and reducing the magnitude of the voltage at said output terminal; a driver stage having an input terminal connected to the output terminal of said input stage and an output terminal; a third FET device in said driver stage, having its drain connected to said output terminal of said driver stage, its source connected to a reference potential, and its gate connected to said input terminal of said driver stage, for separating said load capacitance from said output terminal of said driver; a load impedance in said driver stage connected between the output terminal of said driver stage and a drain voltage; said magnitude of said voltage at said output terminal of said input stage during said second period being sufficiently high to cause said third FET device to conduct, generating a relatively low output voltage at said output terminal of said driver stage; said reduction in the magnitude of said voltage at said output terminal of said input stage during said third period causing said third FET device to stop conduction, generating a relatively high output voltage at said output terminal of said driver stage, having a fast transition due to the lack of capacitive loading thereon; whereby a delayed signal may have a fast transition time.

Claim 22

The circuit of claim 18 wherein said driver stage further comprises: said load impedance having a fourth FET device having its drain connected to said drain voltage and its source connected to said output terminal of said driver stage; a fifth FET device in said driver stage having its gate connected to the gate of said third FET device and its source connected to said reference potential; a sixth FET device in said driver stage having its drain connected to said drain potential, its gate connected to the gate of said fourth FET device, and its source connected to a drain of said fifth FET device; a bootstrap capacitor connected between the gate and the source of said sixth FET device; said gate of said sixth FET device being connected to said input terminal of said input stage; whereby a portion of said input signal precharges said bootstrap capacitor prior to said third period, enabling said driver stage to operate as an unloaded bootstrap driver.

Claim 23

The FET delay circuit of claim 19, which further comprises: a switching stage having an input terminal connected to said input terminal of said input stage and an output terminal connected to said gate of said sixth FET device; a seventh FET device having its source-drain path connected between said input terminal of said switching stage and said output terminal of said switching stage; circuit means in said switching stage connected to the gate of said seventh FET device, for rendering said seventh FET device conductive prior to said third period and non-conductive during said third period; whereby a portion of said input signal may be transmitted to said gate of said sixth FET device to precharge said bootstrap capacitor.

Claim 24

The FET delay circuit of claim 20 wherein said circuit means and said switching stage further comprises: a precharge capacitor connected between the gate and the input terminal of said switching stage; a precharging means connected to the gate of said seventh FET device, for precharging said precharge capacitor prior to said third period, thereby rendering said seventh FET device conductive; an impedance element connected to the gate of said seventh FET device, for slowly discharging said precharged condition of said precharge capacitor prior to said third period; whereby said seventh FET device is conductive prior to said third period and is non-conductive during said third period.

Claim 25

The FET delay circuit of claim 19 wherein said precharge means of said input stage further comprises: a saturated low enhancement mode field effect transistor.

Claim 26

The FET delay circuit of claim 22 wherein said input stage further comprises: an FET device having its source-drain path connected between the gate of said first FET device and a reference potential, with its gate connected to a signal which is on prior to said second period; whereby the gate of said first FET device may be discharged prior to said second period.

Claim 27

The FET delay circuit of claim 19 wherein said precharge means in said input stage further comprises: an enhancement mode field effect transistor having its gate connected to an enabling pulse which is on prior to said second period.

Claim 28

The FET delay circuit of claim 18 wherein said input stage further comprises: an FET device having its source-drain path connected between the gate of said first FET device and a reference potential with its gate connected to a signal which is on prior to said second period; whereby the gate of said first FET device may be discharged prior to said second period.