US3906464A
Expired / Lapsed
US
⏱️ 0.0 years remaining
External data control preset system for inverting cell random access memory
Assignee: Motorola Solutions Inc
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Filing: 1974-06-03
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Granted: 1975-09-16
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Expires: 1994-06-03
Abstract
Abstract A preset conductor adapted to receive a preset signal externally or internally applied thereto presets the data control register of a dynamic MOS random access memory having an array of inverting storage cells therein. A MOSFET is connected between a storage node of each of the data control cells and the data control register and a ground conductor. The preset conductor is connected to the gate electrode of each of the preset MOSFETs.
Inventors
- 👤 William Walter Lattin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C11/403; G11C11/405; G11C11/406
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
70 words
A random access memory comprising an array of inverting storage cell means for storing a logic state therein and inverting said logic state stored in said inverting storage cell means when said inverting storage cell means is sensed and a plurality of data control cells coupled to said storage cell means, and preset means coupled to said data control cell means for presetting the state of said data control cells.
Claim 2
Dependent Claim
70 words
A random access memory comprising an array of inverting storage cell means for storing a logic state therein and inverting said logic state stored in said inverting storage cell means when said inverting storage cell means is sensed and a plurality of data control cells coupled to said storage cell means, and preset means coupled to said data control cell means for presetting the state of said data control cells.
Claim 3
Dependent Claim
32 words
The random access memory as recited in claim 1 wherein said preset means comprises a conductor adapted to receive an externally applied signal for presetting the state of said data control cells.
Claim 4
Dependent Claim
41 words
The random access memory as recited in claim 2 wherein said preset means further comprise separate MOSFETs each having its gate coupled to said conductor and its drain coupled to a storage node, respectively, of one of said data control cells.
Claim 5
Dependent Claim
23 words
The random access memory as recited in claim 3 wherein the source of each of said MOSFETs is coupled to a second conductor.
Claim 6
Dependent Claim
74 words
A MOSFET random access memory including an array of three transistor storage cells arranged as M rows and N columns and N data control cells coupled, respectively, to conductors of said N columns comprising: a separate MOSFET coupled between a ground conductor and a storage node of each of said data control cells; and a present conductor adapted for receiving an externally applied preset signal coupled to the gate of each of said MOSFETs.
Claim 7
Dependent Claim
74 words
A MOSFET random access memory including an array of three transistor storage cells arranged as M rows and N columns and N data control cells coupled, respectively, to conductors of said N columns comprising: a separate MOSFET coupled between a ground conductor and a storage node of each of said data control cells; and a present conductor adapted for receiving an externally applied preset signal coupled to the gate of each of said MOSFETs.
Claim 8
Dependent Claim
97 words
The MOSFET random access memory as recited in claim 5 wherein each of said three transistor storage cells includes a first MOSFET having its drain coupled to a data conductor, its gate connected to a write conductor, and its source connected to a gate of a second MOSFET, said second MOSFET having its source connected to a voltage supply conductor and its drain connected to a source of a third MOSFET in said transistor storage cell, said third transistor storage cell having its gate connected to a read conductor and its drain connected to said data conductor.
Claim 9
Dependent Claim
107 words
The MOSFET random access memory as recited in claim 5 wherein each of said data control cells includes first, second, and third MOSFETs, said first MOSFET having its drain connected to a data control conductor and its gate connected to a write conductor, and its source connected to said storage node, said second MOSFET having its gate connected to said storage node, its source connected to a supply voltage conductor of said MOSFET random access memory and its drain connected to a source of said third MOSFET, said third MOSFET having its gate connected to a read conductor and its drain connected to said data control conductor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |