Patent DE1166419B successfully refreshed from Google Patents.
US3736574A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pseudo-hierarchy memory system
Assignee: International Business Machines Corp
•
Filing: 1971-12-30
•
Granted: 1973-05-29
•
Expires: 1991-12-30
Abstract
Abstract A monolithic memory system for a digital computer comprises an array of monolithic chips arranged in rows. Each chip includes an array of memory cells, associated support circuits, and current reference sources connected to the support circuits. Each of a plurality of power gate drivers has a line connected to the current reference sources of a respective row of chips. One power gate driver is actuated to supply power to the current reference sources of a selected row of chips which includes the selected memory cell to be addressed and the power is uninterruptedly maintained for so long as the successive cells being addressed are within the selected row of chips. When the cell being currently addressed is within a different row of chips, the original power gate driver is deactuated and a new power gate driver is actuated to supply power to the current reference sources of the new row of chips containing the memory cell to be addressed.
Inventors
- 👤 J Gersbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:50
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/414; G11C11/415; G11C11/416
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
215 words
A memory system comprising a plurality of memory cells arranged in groups, means for successively addressing various cells of said plurality, said means including a plurality of support circuit means arranged in groups each associated with a respective group of cells, means for supplying power to only a selected group of support circuit means associated with the group of cells containing the cell to be addressed, means for uninterruptedly maintaining the supply of power to said selected group of support circuit means for so long as the successive cells being addressed are within said group of cells associated with said selected group of support circuit means, means for interrupting the supply of power to said selected group of support circuit means when the cell to be currently addressed is not within said group of cells associated with said selected group of support circuit means, means for supplying power to a newly selected group of support circuit means associated with the different group of cells containing said last-recited cell to be currently addressed, means for periodically timing the operation of said addressing means, and means for delaying the operation of said addressing means when the cell to be currently addressed is not within said group of cells associated with said selected group of support circuit means.
Claim 2
Dependent Claim
215 words
A memory system comprising a plurality of memory cells arranged in groups, means for successively addressing various cells of said plurality, said means including a plurality of support circuit means arranged in groups each associated with a respective group of cells, means for supplying power to only a selected group of support circuit means associated with the group of cells containing the cell to be addressed, means for uninterruptedly maintaining the supply of power to said selected group of support circuit means for so long as the successive cells being addressed are within said group of cells associated with said selected group of support circuit means, means for interrupting the supply of power to said selected group of support circuit means when the cell to be currently addressed is not within said group of cells associated with said selected group of support circuit means, means for supplying power to a newly selected group of support circuit means associated with the different group of cells containing said last-recited cell to be currently addressed, means for periodically timing the operation of said addressing means, and means for delaying the operation of said addressing means when the cell to be currently addressed is not within said group of cells associated with said selected group of support circuit means.
Claim 3
Dependent Claim
26 words
A memory system as set forth in claim 1 wherein each of said support circuit means comprises decoder means for selecting the cell to be addressed.
Claim 4
Dependent Claim
31 words
A memOry system as set forth in claim 1 wherein each of said support circuit means comprises data input/output circuit means for writing into and reading out of the addressed cell.
Claim 5
Dependent Claim
33 words
A memory system as set forth in claim 1 wherein said addressing means includes a word matrix and a bit matrix, and said support circuit means includes decoder means for said two matrices.
Claim 6
Dependent Claim
29 words
A memory system as set forth in claim 4 wherein said support circuit means includes data input/output circuit means for writing into and reading out of the addressed cell.
Claim 7
Dependent Claim
162 words
A monolithic memory system comprising an array of monolithic chips arranged in groups, each of said chips including an array of memory cells and support circuits associated therewith, means for successively addressing selected cells, means for supplying power to only the support circuits of a selected group of chips including the memory cell array having the selected cell to be addressed, and means for uninterruptedly maintaining the supply of power to the support circuits of said selected group of chips for so long as the successive cells being addressed are within said selected group of chips, means for interrupting the supply of power to the support circuits of said selected group of chips when the cell to be currently addressed is not within said selected group of chips, and means for supplying power to the support circuits of a newly selected group of chips containing said cell to be currently addressed, and means for periodically timing the operation of said addressing means.
Claim 8
Dependent Claim
162 words
A monolithic memory system comprising an array of monolithic chips arranged in groups, each of said chips including an array of memory cells and support circuits associated therewith, means for successively addressing selected cells, means for supplying power to only the support circuits of a selected group of chips including the memory cell array having the selected cell to be addressed, and means for uninterruptedly maintaining the supply of power to the support circuits of said selected group of chips for so long as the successive cells being addressed are within said selected group of chips, means for interrupting the supply of power to the support circuits of said selected group of chips when the cell to be currently addressed is not within said selected group of chips, and means for supplying power to the support circuits of a newly selected group of chips containing said cell to be currently addressed, and means for periodically timing the operation of said addressing means.
Claim 9
Dependent Claim
42 words
A memory system as set forth in claim 6 and comprising means for delaying the operation of said addressing means when the cell to be currently addressed is not within a cell array on one of said original selected group of chips.
Claim 10
Dependent Claim
23 words
A memory system as set forth in claim 7 wherein said support circuits comprise decoder means for selecting the cell to be addressed.
Claim 11
Dependent Claim
28 words
A memory system as set forth in claim 8 wherein said support circuits comprise data input/output circuit means for writing into and reading out of the addressed cell.
Claim 12
Dependent Claim
49 words
A memory system as set forth in claim 6 wherein said addressing means includes on each chip a word matrix and a bit matrix each having an array of operative elements, and said support circuits include decoder means for selecting an operative element of each of said two matrices.
Claim 13
Dependent Claim
31 words
A memory system as set forth in claim 4 wherein said support circuits on each chip include a data input/output circuit for writing into and reading out of the addressed cell.
Claim 14
Dependent Claim
86 words
A memory system as set forth in claim 13 and comprising means for deactuating said power gate driver to interrupt the supply of power to said support circuits of said selected row of chips when the cell to be currently addressed is not within a cell array on one of said selected row of chips, and means for actuating a different power gate driver to supply power to a newly selected row of chips having the cell array including said last-recited cell to be currently addressed.
Claim 15
Dependent Claim
167 words
A monolithic memory system comprising an array of monolithic chips arranged in a plurality of rows, each of said chips including an array of memory cells and support circuits associated therewith, a plurality of power gate drivers each having a power gate line, means connecting each of said power gate lines to the support circuits of a respective row of said chips, means for successively addressing selected cells, means for actuating a power gate driver to supply power to the support circuits of a selected row of chips which includes the selected memory cell to be addressed, means for uninterruptedly maintaining the supply of power to said support circuits of said selected row of chips for so long as the successive cells being addressed are within said selected row of chips, means for periodically timing the operation of saId addressing means, and means for delaying the operation of said addressing means when the cell to be currently addressed is not within said original selected row of chips.
Claim 16
Dependent Claim
167 words
A monolithic memory system comprising an array of monolithic chips arranged in a plurality of rows, each of said chips including an array of memory cells and support circuits associated therewith, a plurality of power gate drivers each having a power gate line, means connecting each of said power gate lines to the support circuits of a respective row of said chips, means for successively addressing selected cells, means for actuating a power gate driver to supply power to the support circuits of a selected row of chips which includes the selected memory cell to be addressed, means for uninterruptedly maintaining the supply of power to said support circuits of said selected row of chips for so long as the successive cells being addressed are within said selected row of chips, means for periodically timing the operation of saId addressing means, and means for delaying the operation of said addressing means when the cell to be currently addressed is not within said original selected row of chips.
Claim 17
Dependent Claim
26 words
A memory system as set forth in claim 13 wherein said support circuits on each chip comprise decoder means for selecting the cell to be addressed.
Claim 18
Dependent Claim
31 words
A memory system as set forth in claim 13 wherein said support circuits on each chip comprise data input/output circuit means for writing into and reading out of the addressed cell.
Claim 19
Dependent Claim
32 words
A memory system as set forth in claim 13 wherein said addressing means includes a word matrix and a bit matrix, and said support circuits include decoder means for said two matrices.
Claim 20
Dependent Claim
31 words
A memory system as set forth in claim 16 wherein said support circuits on each chip include a data input/output circuit for writing into and reading out of the addressed cell.
Claim 21
Dependent Claim
87 words
A memory system as set forth in claim 19 and comprising means for interrupting the supply of power to the current reference source means of said selected row of chips when the cell to be currently addressed is not within a cell array on one of said selected row, and means for actuating a different power gate driver to supply power to the current reference source means of a newly selected row of chips which has the cell array containing said last-recited cell to be currently addressed.
Claim 22
Dependent Claim
183 words
A monolithic memory system comprising an array of monolithic chips arranged in a plurality of rows, each of said chips including an array of memory cells and support circuits associated therewith, each of said chips including current reference source means connected to said support circuits, a plurality of power gate drivers each having a power gate line connected to the current reference source means of a respective row of said chips, means for successively addressing selected cells, means for actuating a power gate driver to supply power to the current reference source means of a selected row of chips which includes the selected memory cell to be addressed, means for uninterruptedly maintaining the supply of power to said current reference source means of said selected row of chips for so long as the successive cells being addressed are within said selected row of chips, means for periodically timing the operation of said addressing means, and means for delaying the operation of said addressing means when the cell to be currently addressed is not within a cell array on said selected row of chips.
Claim 23
Dependent Claim
183 words
A monolithic memory system comprising an array of monolithic chips arranged in a plurality of rows, each of said chips including an array of memory cells and support circuits associated therewith, each of said chips including current reference source means connected to said support circuits, a plurality of power gate drivers each having a power gate line connected to the current reference source means of a respective row of said chips, means for successively addressing selected cells, means for actuating a power gate driver to supply power to the current reference source means of a selected row of chips which includes the selected memory cell to be addressed, means for uninterruptedly maintaining the supply of power to said current reference source means of said selected row of chips for so long as the successive cells being addressed are within said selected row of chips, means for periodically timing the operation of said addressing means, and means for delaying the operation of said addressing means when the cell to be currently addressed is not within a cell array on said selected row of chips.
Claim 24
Dependent Claim
23 words
A memory system as set forth in claim 19 wherein said support circuits comprise decoder means for selecting the cell to be addressed.
Claim 25
Dependent Claim
28 words
A memory system as set forth in claim 20 wherein said support circuits comprise data input/output circuit means for writing into and reading out of the addressed cell.
Claim 26
Dependent Claim
32 words
A memory system as set forth in claim 19 wherein said addressing means includes a word matrix and a bit matrix, and said support circuits include decoder means for said two matrices.
Claim 27
Dependent Claim
28 words
A memory system as set forth in claim 19 wherein said support circuits include a data input/output circuit for writing into and reading out of the addressed cell.
References Cited (Backward Citations)
US3317902A
Cited
US3599182A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-28 | 1976-11-27 | 1977-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-28 | 1980-11-27 | 1981-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-28 | 1984-11-27 | 1985-05-29 | $7700.00 | Window Closed / Lapsed |