US3681764A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low power memory system
Assignee: Northrop Grumman Guidance and Electronics Co Inc
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Filing: 1971-03-15
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Granted: 1972-08-01
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Expires: 1991-03-15
Abstract
Abstract A memory system is disclosed which includes input means for receiving a binary word to be stored, in which the word comprises a plurality of bits each having either a ''''one'''' state or a ''''zero'''' state. Counting means are provided for counting the number of bits in the ''''one'''' state and for providing an output control signal whenever the number of such bits exceeds one-half of the number of bits in the word. The output signal of the counting means controls an input complementing gate which receives the word from the aforementioned input means and which places the word into its complemented state, that is into a state in which all of the ''''one'''' bits are changed into ''''zero'''' and all of the ''''zero'''' bits are changed into ''''one'''' bits, whenever the control signal is applied to the complementing gate. The word, in either its complemented or its uncomplemented state, is then applied to a conventional memory, and an additional control bit is also applied to the memory to indicate the complementary state of the word as being stored in the memory.
Inventors
- 👤 Theodore A Conant Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/06; G11C11/06007
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
189 words
A memory system comprising, in combination: input means for receiving a binary word to be stored, said word comprising a plurality of bits each having either a first state or a second state, counting means for providing an output signal whenever the number of bits in said word having said first state exceeds a predetermined number, input complementing gate means whose output signals are the complement of its input signals if a control signal is applied to said input gate means and whose output signals are the same as its input signals if no control signal is applied to said input gate means, means for applying said word from said input means to said input gate means as the input signals to said input gate means, means for applying a control signal to said input gate means which is indicative of the state of the output signal from said counting means, a memory, means for applying the output signals of said input gate means to said memory, and means for storing a control bit in said memory indicating the complementary state of said word as stored in said memory.
Claim 2
Dependent Claim
189 words
A memory system comprising, in combination: input means for receiving a binary word to be stored, said word comprising a plurality of bits each having either a first state or a second state, counting means for providing an output signal whenever the number of bits in said word having said first state exceeds a predetermined number, input complementing gate means whose output signals are the complement of its input signals if a control signal is applied to said input gate means and whose output signals are the same as its input signals if no control signal is applied to said input gate means, means for applying said word from said input means to said input gate means as the input signals to said input gate means, means for applying a control signal to said input gate means which is indicative of the state of the output signal from said counting means, a memory, means for applying the output signals of said input gate means to said memory, and means for storing a control bit in said memory indicating the complementary state of said word as stored in said memory.
Claim 3
Dependent Claim
107 words
The memory system of claim 1 which further comprises: output complementing gate means whose output signals are the complement of its input signals if a control signal is applied to said output gate means and whose output signals are the same as its input signals if no control signal is applied to said output gate means, output means for applying said word in its complementary state as stored in said memory to said output gate means as the input signal to said output gate means, and means for applying a control signal to said output gate means which is indicative of the state of said control bit.
Claim 4
Dependent Claim
45 words
The memory system of claim 2 which further includes complementary control means for generating a control signal for said input gate responsive to the output signal of said counting means and for generating a control signal for said output gate responsive to said control bit.
Claim 5
Dependent Claim
71 words
The memory system of claim 3 in which said output means comprises: a register having a plurality of stages each having input and output terminals, means for applying each bit of said word in its complementary state as stored in said memory to an input terminal of a respective one of said stages of said register, and means for applying the output signals from said register to said output complementary gate.
Claim 6
Dependent Claim
43 words
The memory system of claim 4 in which said input means comprises said register and means for applying each bit of said word as received at said memory system to an input terminal of a respective one of said stages of said register.
Claim 7
Dependent Claim
81 words
The memory system of claim 5 in which said input complementing gate means comprises a plurality of EXCLUSIVE OR gates each having a first and second input terminal and an output terminal, means connecting said first input terminals of said EXCLUSIVE OR gates to receive a control signal from said complementing control means, and means connecting each of said second input terminals of said EXCLUSIVE OR gates to the output terminal of a respective one of the stages of said register.
Claim 8
Dependent Claim
105 words
The memory system of claim 6 in which the bits of said word are received in series, the stages of said register are connected in series to form a shift register and said word is applied to input terminals of the first stage of said shift register and in which said output complementing gate comprises an EXCLUSIVE OR gate having a first and second input terminal and an output terminal, means connecting said first input terminal to receive a control signal from said complementing control means, and means connecting said second input terminal to the output terminal of the final stage of said shift register.
Claim 9
Dependent Claim
33 words
The memory system of claim 7 in which said counting means comprises a preset binary counter and means applying all of the bits of said word having said first state of said counter.
Claim 10
Dependent Claim
101 words
The memory system of claim 6 in which the bits of said word are received in parallel and are each applied to the input terminals of a respective one of the stages of said register and in which said output complementing gate means comprises a plurality of EXCLUSIVE OR gates each having a first and second input terminal and an output terminal, means connecting said first input terminals to receive a control signal from said complementing control means and means connecting each of said second input terminals to the output terminal of a respective one of the stages of said register.
Claim 11
Dependent Claim
44 words
The memory system of claim 9 in which said counting means comprises a resister adder, means applying all of the bits of said word to said adder, and means for obtaining an output signal whenever the output of said adder exceeds a predetermined value.
References Cited (Backward Citations)
US3170142A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-01 | 1976-01-31 | 1976-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-01 | 1980-01-31 | 1980-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-01 | 1984-01-31 | 1984-08-01 | $7700.00 | Window Closed / Lapsed |