Overload protection circuit for output driver

Claim 2

The combination comprising: a transistor having first and second electrodes defining the ends of its conduction path and a control electrode; a power terminal adapted to receive an operating potential; an output terminal; negligible impedance means connecting the conduction path of said transistor between said power and output terminals; means independent of the voltages at said power and output terminals for selectively applying a turn on signal to the control electrode of said transistor for causing a flow of current between said power and output terminals through the conduction path of said transistor and for driving said output terminal toward the operating potential at said power terminal; and means coupled to the control electrode of said transistor responsive to the application of said turn on signal and to the potential at said output terminal for substantially decreasing current conduction to a value greater than zero through said transistor only after a given time period if the voltage at said output terminal does not reach a predetermined value within said given time period.

Claim 3

The combination as claimed in claim 1 wherein said means coupled to the control electrode of said transistor responsive to the application of said turn on signal and to the potential at said output terminal for substantially decreasing current conduction through said transistor if the potential at said output terminal does not reach a predetermined value within a given time period after the turn on of said transistor, includes a delay network for decreasing current in said transistor a time T D after it is turned on; where T D is less than a time T TH , where T TH defines the point in time at which said transistor may be damaged if high level conduction persists through the transistor; and negative feedback means for controlling and limiting the decrease in the conductivity of said transistor to a value greater than zero.

Claim 4

The combination as claimed in claim 1 wherein said output terminal is adapted to drive a given load; wherein the time for said transistor to charge said output terminal to said predetermined value when said given load is connected thereto is T N ; wherein said transistor has a thermal time constant which defines the point at which said transistor may be damaged if high level conduction through said transistor persists for a period of time T TH ; wherein said given time period is a time T D , where T D is greater than T N and less than T TH ; and wherein said means coupled to the control electrode of said transistor includes a delay network for decreasing conduction through said transistor a time T D after said transistor is turned on if said output terminal does not reach said predetermined value.

Claim 5

The combination as claimed in claim 1 wherein said transistor is an output transistor; and wherein said means coupled to the control electrode of said transistor responsive to the application of said turn on signal and to the potential at said output terminal includes: (a) a second transistor having first and second electrodes defining the ends of a conduction path and a control electrode; (b) means connecting the conduction path of said second transistor between said power terminal and the control electrode of said output transistor; and (c) means for applying a turn on signal to the control electrode of said second transistor within said given time period after the turn on of said output transistor if the potential at said output terminal does not reach said predetermined value; said second transistor when turned on producing a signal at the control electrode of said output transistor having a polarity and magnitude to decrease the conductivity of said output transistor.

Claim 6

The combination as claimed in claim 4 wherein said means for applying a turn on signal to the control electrode of said second transistor includes: (a) a third transistor having its conduction path connected between the control electrode of said second transistor and said power terminal; said third transistor being biased to function as a resistive element; (b) a fourth transistor having its conduction path connected between the control electrode of said second transistor and said output terminal; and (c) means for applying a turn on signal to the control electrode of said fourth transistor when said output transistor is turned on.

Claim 7

The combination as claimed in claim 4 wherein said means for applying a turn on signal to the control electrode of said second transistor includes: (a) a third transistor having its conduction path connected between the control electrode of said second transistor and said power terminal; said third transistor being biased to function as a resistive element; (b) a fourth transistor having its conduction path connected between the control electrode of said second transistor and the control electrode of said output transistor; and (c) means for coupling the signal at said output terminal to the control electrode of said fourth transistor.

Claim 8

The combination as claimed in claim 1 wherein said transistor is an output transistor; and wherein said means responsive to the application of said turn on signal and to the potential at said output terminal includes: (a) a second transistor having first and second electrodes defining the ends of a conduction path and a control electrode; (b) means applying a signal indicative of the turn on of said output transistor to the control electrode of said second transistor; and (c) means connecting one of the first and second electrodes of said second transistors to said output terminal for causing said second transistor to conduct in the voltage follower mode.

Claim 9

The combination as claimed in claim 7 wherein said means responsive to the application of said turn on signal and to the potential at said output terminal also includes a delay network connected to the other one of the first and second electrodes of said second transistor, said delay network for producing a given output a time T D after said second transistor is turned on.

Claim 10

The combination as claimed in claim 8 wherein said means responsive to the application of said turn on signal and to the potential at said output terminal also includes a third transistor connected at its control electrode to said delay network and responsive to said given output for applying a potential to the control electrode of said output transistor having a polarity and magnitude to decrease conduction through said output transistor.

Claim 11

The combination as claimed in claim 9 wherein said output transistor is of one conductivity type and said second transistor is of different conductivity type.

Claim 12

The combination as claimed in claim 10 wherein said first, second and third transistors are insulated-gate field effect transistors, wherein said first and third transistors are connected at their source electrodes to said power terminal; wherein said third transistor is connected at its drain to the gate of said first transistor, and wherein said second transistor is connected at its source to said output terminal and at its drain to the gate of said third transistor.

Claim 13

The combination as claimed in claim 11 wherein said delay network includes: (a) the conduction path of a fourth transistor having its conduction path connected between the drain of said second transistor and said power terminal; and (b) the capacitance present between the drain of said second transistor and said power terminal.

Claim 14

The combination as claimed in claim 1 wherein said transistor is a first output transistor; wherein said means for selectively applying a turn on signal to the control electrode of said first transistor includes a first inverter; wherein said means responsive to the application of said turn on signal and to the potential at said output terminal includes, second, third and fourth inverting means; each inverting means having an input and an output; wherein said second inverting means is connected at its input to the output of said first inverting means and at its output to the input of said third inverting means; wherein said third inverting means includes a transistor having its control electrode connected to the input of said third inverting means, one end of its conduction path connected to said output terminal, and the other end of its conduction path connected to the output of said third inverting means; and means connecting the input of said fourth inverting means to the output of said third inverting means and the output of said fourth inverting means to the input of said second inverter means.

Claim 15

The combination as claimed in claim 1 wherein said power terminal is a first power terminal and further including a second power terminal; said first and second power terminals adapted to receive an operating potential; wherein said transistor is a first transistor; and further including a second transistor having its conduction path connected between said second power terminal and said output terminal; means for selectively applying a turn on signal to the control electrode of said second transistor for passing a current between said second power terminal and said output terminal and for clamping said output terminal to the potential at said second power terminal; and means coupled to the control electrode of said second transistor responsive to the application of a turn on signal to it and to the potential at said output terminal for substantially decreasing current conduction through said second transistor if the potential at said output terminal does not reach a predetermined value within a given time period after the turn on of said second transistor.