US5117129A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cmos off chip driver for fault tolerant cold sparing
Assignee: BAE Systems Information and Electronic Systems Integration Inc
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Filing: 1990-10-16
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Granted: 1992-05-26
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Expires: 2010-10-16
Abstract
Abstract A full swing CMOS logic circuit provides fault tolerant, cold sparing of VLSI logic devices attached to a high speed bus. P-channel FET transistors are formed in an N-well which has a biasing transistor which effectively decouples the circuit when the circuit is not powered. The input/output interface of the cold spares have a high impedance and do not corrupt an interconnected electronic bus. The final drive transistors are reverse biased or clamped to zero to prevent any leakage paths.
Inventors
- 👤 Joseph A. Hoffman
- 👤 Derwin L. Jallice
- 👤 Yogishwar K. Puri
- 👤 Randall G. Richards
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:16
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; H; H10; H10D; H10D89/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
136 words
A CMOS Off Chip Driver circuit comprising: an N-well biasing transistor having a source, drain and gate the source being connected to an N-well, the drain connected to a power supply and the gate connected between an input/output pad of the off chip driver circuit and a pair of CMOS final drive transistors; the pair of CMOS final drive transistors connected to a precharge CMOS circuit having an input and output, the final drive transistors providing amplification of the precharge CMOS circuit output; a pad signal electronically connected to the input of the precharge CMOS drive circuit and to a tri-state enable, the tri-state enable selecting the active state of the input/output pad; whereby the N-well biasing transistor electrically biases the N-well to effectively prevent any leakage current when the circuit is in an unpowered state.
Claim 2
Dependent Claim
136 words
A CMOS Off Chip Driver circuit comprising: an N-well biasing transistor having a source, drain and gate the source being connected to an N-well, the drain connected to a power supply and the gate connected between an input/output pad of the off chip driver circuit and a pair of CMOS final drive transistors; the pair of CMOS final drive transistors connected to a precharge CMOS circuit having an input and output, the final drive transistors providing amplification of the precharge CMOS circuit output; a pad signal electronically connected to the input of the precharge CMOS drive circuit and to a tri-state enable, the tri-state enable selecting the active state of the input/output pad; whereby the N-well biasing transistor electrically biases the N-well to effectively prevent any leakage current when the circuit is in an unpowered state.
Claim 3
Dependent Claim
40 words
The CMOS off chip driver circuit of claim 1 wherein leakage control transistors are connected between the tri-state enable and the CMOS final drive transistor to dissipate any stored charge due to the previous logical state of the input/output pad.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |