US4975598A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Temperature, voltage, and process compensated output driver
Assignee: Intel Corp
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Filing: 1988-12-21
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Granted: 1990-12-04
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Expires: 2008-12-21
Abstract
Abstract An output driver for high performance integrated circuits. The driver dynamically compensates for variations in temperature, voltage and process. To perform the compensation, the driver is divided into two parts: static and transient. The static part is used to maintain the DC level. The transient part is active only during logic 0 to 1 and 1 to 0 transitions and is used only to assist the static part during such transitions. A closed loop feedback technique is used to compensate the driver for temperature, process, and voltage variations; specifically, a scaled down version of an output driver is used to monitor speed variations due to temperature, process, and voltage, the output of which is fed back to the output driver which then performs the necessary compensation.
Inventors
- 👤 Shekhar Borkar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:05
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
193 words
In a large scale integrated circuit formed by a predetermined process including at least one output driver, said circuit comprising: compensating means coupled to said output driver for compensating the performance of the output driver due to variations in temperature, voltage and the process, and wherein said at least one output driver includes: static means coupled to a driver input to said output driver and said compensating means for generating an output of said output driver as a function of said driver input; monitoring means coupled to said static means for monitoring said static means and generating first and second signals indicating that said output is beginning to change from a first logic level to a second logic level; transient means coupled to said static means, said monitoring means and said compensating means operating substantially only during transitions from said first logic level to said second logic level for assisting the output of said static means to reach the second logic level and thereby reduce a rate of change of current flowing through said output driver, whereby the output of said static means is compensated due to variations in temperature, voltage and process.
Claim 2
Dependent Claim
193 words
In a large scale integrated circuit formed by a predetermined process including at least one output driver, said circuit comprising: compensating means coupled to said output driver for compensating the performance of the output driver due to variations in temperature, voltage and the process, and wherein said at least one output driver includes: static means coupled to a driver input to said output driver and said compensating means for generating an output of said output driver as a function of said driver input; monitoring means coupled to said static means for monitoring said static means and generating first and second signals indicating that said output is beginning to change from a first logic level to a second logic level; transient means coupled to said static means, said monitoring means and said compensating means operating substantially only during transitions from said first logic level to said second logic level for assisting the output of said static means to reach the second logic level and thereby reduce a rate of change of current flowing through said output driver, whereby the output of said static means is compensated due to variations in temperature, voltage and process.
Claim 3
Dependent Claim
116 words
The circuit defined by claim 1 wherein said static means comprises: a P transistor driver coupled to an N transistor driver; a first predriver having an input coupled to said driver input and having an output coupled to said P transistor driver and a second predriver having an input coupled to said driver input and having an output coupled to said N transistor driver a first at least one assist transistor coupled between the input and output of said first predriver controlling the switching speed of said P transistor driver; a second at least one assist transistor coupled between the input and output of said second predriver controlling the switching speed of said N transistor driver.
Claim 4
Dependent Claim
81 words
The circuit defined by claim 2 wherein said monitoring means comprises: a first at least one transistor coupled to the output of said first predriver for generating said first signal for use by said transient means when said first predriver output reaches a predetermined trip point; a second at least one transistor coupled to the output of said second predriver for generating said second signal for use by said transient means when said second predriver output reaches a predetermined trip point.
Claim 5
Dependent Claim
26 words
The circuit defined by claim 3 wherein the predetermined trip point of each of said first and second transistors is approximately one-half of a supply voltage.
Claim 6
Dependent Claim
150 words
The circuit defined by claim 1 wherein said transient means comprises: a P transistor transient driver coupled to an N transistor transient driver; a first transient predriver having a first input coupled to said driver input and a second input for receiving said first signal and having an output coupled to said P transistor transient driver and a second transient predriver having a first input coupled to said driver input and a second input for receiving said second signal and having an output coupled to said N transistor transient driver; a first at least one assist transistor coupled between the second input and the output of said first transient predriver controlling the switching speed of said P transistor transient driver; a second at least one assist transistor coupled between the second input and the output of said second transient predriver controlling the switching speed of said N transistor transient driver.
Claim 7
Dependent Claim
24 words
The circuit defined by claim 5 wherein said first transient predriver is a NAND gate and said second transient predriver is a NOR gate.
Claim 8
Dependent Claim
166 words
The circuit defined by claim 1 wherein said compensating means comprises: precharge means for charging a dummy load to a supply voltage during a first phase of a clock signal; driver means for discharging the charge on said dummy load during a second phase of said clock signal; predriver means for charging an input of said driver means with a feedback signal; level detector means coupled to said dummy load for detecting when the voltage on said dummy load falls below a predetermined voltage; latch means coupled to said level detector means and a first capacitor means for latching the output of said level detector means during the second phase of said clock signal and charging said first capacitor with the value of said latched output; transfer gate means coupled to said first capacitor means for transferring the charge on said first capacitor means to a second capacitor means, wherein the output of said transfer gate means is also said feedback signal to said predriver means.
Claim 9
Dependent Claim
26 words
The circuit defined by claim 7 wherein said precharge means comprises an N transistor and a P transistor whose gates are coupled to said clock signal.
Claim 10
Dependent Claim
41 words
The circuit defined by claim 7 wherein said driver means comprises a transistor whose gate is coupled to said predriver means and whose source is coupled to said precharge means and said dummy load and whose drain is coupled to ground.
Claim 11
Dependent Claim
37 words
The circuit defined by claim 7 wherein said predriver means comprises at least one transistor of opposite polarity to that of said driver means and having an input coupled to said clock signal and said feedback signal.
Claim 12
Dependent Claim
27 words
The circuit defined by claim 7 wherein said level detector means comprises at least one transistor whose gate is coupled to an output of said driver means.
Claim 13
Dependent Claim
49 words
The circuit defined by claim 7 wherein said latch means comprises first and second pairs of transistors, each transistor pair having two transistors of opposite polarity coupled in parallel whose gates are coupled to said clock signal, and at least one inverter coupled between said two pairs of transistors.
Claim 14
Dependent Claim
33 words
The circuit defined by claim 7 wherein said transfer gate means comprises a transistor pair having two transistors of opposite polarity coupled in parallel and whose gates are coupled to said clock signal.
References Cited (Backward Citations)
US4473762A
Cited
US4584492A
Cited
US4691127A
Cited
US4638187B1
Cited
US4638187A
Cited
US4785203A
Cited
US4749882A
Cited
US4760292A
Cited
US4829199A
Cited
US4777389A
Cited
US4855623A
Cited
US4820942A
Cited
US4857770A
Cited
US4877980A
Cited
US4866308A
Cited
US4880997A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-03 | 1994-06-04 | 1994-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-03 | 1998-06-04 | 1998-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-03 | 2002-06-04 | 2002-12-04 | $7700.00 | Window Closed / Lapsed |