Time variant drive circuit for high speed bus driver to limit oscillations or ringing on a bus

Claim 2

A time variant drive circuit comprising: an N-channel MOS driver transistor coupled to a first circuit, said driver transistor controlling voltage applied to said first circuit in response to a time variant drive signal; a first field-effect transistor having a second terminal coupled to a gate of said driver transistor and having a channel with a width-to-length ratio such that a high digital drive signal applied to a first terminal of said first field-effect transistor produces a gradually increasing voltage at said second terminal of said first field-effect transistor, leveling off at a maximum drive signal voltage; and a second field-effect transistor having a second terminal coupled to said gate of said driver transistor and having a channel with a width-to-length ratio such that said high digital drive signal applied to a first terminal of said second field-effect transistor rapidly produces a certain voltage at said second terminal of said second field-effect transistor, said certain voltage being lower than said maximum drive signal voltage so as not to cause objectionable ringing on a bus coupling said driver transistor to said first circuit.

Claim 3

A time variant drive circuit as in claim 1 wherein said second field-effect transistor has a channel of a conductivity type opposite to a channel of said first field effect transistor.

Claim 4

A time variant drive circuit comprising: a P-channel MOS driver transistor coupled to a first circuit, said driver transistor controlling voltage applied to said first circuit in response to a time variant drive signal; a first field-effect transistor having a second terminal coupled to a gate of said driver transistor and having a channel with a width-to-length ratio such that a low digital drive signal applied to a first terminal of said first field-effect transistor produces a gradually decreasing voltage at said second terminal of said first field-effect transistor, leveling off at a minimum drive signal voltage; and a second field-effect transistor having a second terminal coupled to a gate of said driver transistor and having a channel with a width-to-length ratio such that said low digital drive signal applied to a first terminal of said second field-effect transistor rapidly produces a certain voltage at said second terminal of said second field-effect transistor, said certain voltage being higher than said minimum drive signal voltage so as not to cause objectionable ringing on a bus coupling said driver transistor to said first circuit.

Claim 5

A time variant drive circuit comprising: a P-channel MOS driver transistor coupled to a first circuit, said driver transistor controlling voltage applied to said first circuit in response to a time variant drive signal; a first field-effect transistor having a second terminal coupled to a gate of said driver transistor and having a channel with a width-to-length ratio such that a low digital drive signal applied to a first terminal of said first field-effect transistor produces a gradually decreasing voltage at said second terminal of said first field-effect transistor, leveling off at a minimum drive signal voltage; and a second field-effect transistor having a second terminal coupled to a gate of said driver transistor and having a channel with a width-to-length ratio such that said low digital drive signal applied to a first terminal of said second field-effect transistor rapidly produces a certain voltage at said second terminal of said second field-effect transistor, said certain voltage being higher than said minimum drive signal voltage so as not to cause objectionable ringing on a bus coupling said driver transistor to said first circuit.

Claim 6

A time variant drive circuit as in claim 3 wherein said second field-effect transistor has a channel of a conductivity type opposite to a channel of said first field-effect transistor.

Claim 7

A time variant driver circuit comprising: an N-channel MOS driver transistor coupled to a first circuit, said driver transistor controlling voltage applied to said first circuit in response to a time variant drive signal; and an N-channel and P-channel MOS transistor connected so that said drive signal is simultaneously applied to a drain of said N-channel MOS transistor and a source of said P-channel MOS transistor, and connected so that a gate of said driver transistor is connected to a source of said N-channel MOS transistor and a drain of said P-channel MOS transistor, said N-channel MOS transistor having a construction and a gate bias voltage so as to provide a voltage at said gate of said driver transistor, upon application of said digital drive signal to said N-channel MOS transistor, which will not produce objectionable ringing on a bus coupled between said driver transistor and said first circuit, and said P-channel MOS transistor having a construction and gate voltage so as to provide a gradually increasing voltage at said gate of said driver transistor, upon application of said digital drive signal to said P-channel MOS transistor, wherein said gradually increasing voltage continues to increase until equal to a maximum drive signal voltage.

Claim 8

A time variant driver circuit comprising: an N-channel MOS driver transistor coupled to a first circuit, said driver transistor controlling voltage applied to said first circuit in response to a time variant drive signal; and an N-channel and P-channel MOS transistor connected so that said drive signal is simultaneously applied to a drain of said N-channel MOS transistor and a source of said P-channel MOS transistor, and connected so that a gate of said driver transistor is connected to a source of said N-channel MOS transistor and a drain of said P-channel MOS transistor, said N-channel MOS transistor having a construction and a gate bias voltage so as to provide a voltage at said gate of said driver transistor, upon application of said digital drive signal to said N-channel MOS transistor, which will not produce objectionable ringing on a bus coupled between said driver transistor and said first circuit, and said P-channel MOS transistor having a construction and gate voltage so as to provide a gradually increasing voltage at said gate of said driver transistor, upon application of said digital drive signal to said P-channel MOS transistor, wherein said gradually increasing voltage continues to increase until equal to a maximum drive signal voltage.

Claim 9

A time variant drive circuit as in claim 5 wherein said gate voltage of said P-channel MOS transistor is at ground potential.

Claim 10

A CMOS drive circuit for driving a logic state of a bus high or low in response to a drive signal produced by a pre-driver stage and applied to said drive circuit, said drive circuit comprising: a P-channel MOS (PMOS) driver transistor and an N-channel MOS (NMOS) driver transistor coupled in series between a high state voltage source and a ground wherein said PMOS driver transistor has a source connected to said high state voltage source and said NMOS driver transistor has a drain connected to a drain of said PMOS driver transistor and a source connected to a ground, and wherein said bus is coupled to a common point of said PMOS and NMOS driver transistors; a first circuit for producing a time variant signal coupled between a pre-driver stage for said PMOS driver transistor and a gate of said PMOS driver transistor, said first circuit comprising a first field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that a low drive signal produced by said pre-driver stage for said PMOS transistor applied to a first terminal of said first field-effect transistor produces a gradually decreasing voltage at a second terminal of said first field-effect transistor, said gradually decreasing voltage leveling off at a minimum voltage, for application to said PMOS driver transistor, said first circuit further comprising a second field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that said low drive signal produced by said pre-driver stage for said PMOS transistor applied to a first terminal of said second field-effect transistor rapidly produces a certain voltage at a second terminal of said second field-effect transistor for application to said gate of said PMOS driver transistor, said certain voltage being higher than said minimum voltage so as to not cause objectional ringing on said bus coupled to said PMOS driver transistor; a second circuit for producing a time variant signal coupled between a pre-driver stage for said NMOS driver transistor and a gate of said NMOS driver transistor, said second circuit comprising a third field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that a high drive signal produced by said pre-driver stage for said NMOS transistor applied to a first terminal of said third field-effect transistor produces a gradually increasing voltage at a second terminal of said third field-effect transistor, said gradually increasing voltage leveling off at a maximum voltage, for application to said NMOS driver transistor, said second circuit further comprising a fourth field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that said high drive signal produced by said pre-driver stage for said NMOS transistor applied to a first terminal of said fourth field-effect transistor rapidly produces a certain voltage at a second terminal of said fourth field-effect transistor for application to said gate of said NMOS driver transistor, said certain voltage being lower than said high drive signal voltage so as not to cause objectional ringing on said bus coupled to said NMOS driver transistor.

Claim 11

A CMOS drive circuit for driving a logic state of a bus high or low in response to a drive signal produced by a pre-driver stage and applied to said drive circuit, said drive circuit comprising: a P-channel MOS (PMOS) driver transistor and an N-channel MOS (NMOS) driver transistor coupled in series between a high state voltage source and a ground wherein said PMOS driver transistor has a source connected to said high state voltage source and said NMOS driver transistor has a drain connected to a drain of said PMOS driver transistor and a source connected to a ground, and wherein said bus is coupled to a common point of said PMOS and NMOS driver transistors; a first circuit for producing a time variant signal coupled between a pre-driver stage for said PMOS driver transistor and a gate of said PMOS driver transistor, said first circuit comprising a first field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that a low drive signal produced by said pre-driver stage for said PMOS transistor applied to a first terminal of said first field-effect transistor produces a gradually decreasing voltage at a second terminal of said first field-effect transistor, said gradually decreasing voltage leveling off at a minimum voltage, for application to said PMOS driver transistor, said first circuit further comprising a second field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that said low drive signal produced by said pre-driver stage for said PMOS transistor applied to a first terminal of said second field-effect transistor rapidly produces a certain voltage at a second terminal of said second field-effect transistor for application to said gate of said PMOS driver transistor, said certain voltage being higher than said minimum voltage so as to not cause objectional ringing on said bus coupled to said PMOS driver transistor; a second circuit for producing a time variant signal coupled between a pre-driver stage for said NMOS driver transistor and a gate of said NMOS driver transistor, said second circuit comprising a third field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that a high drive signal produced by said pre-driver stage for said NMOS transistor applied to a first terminal of said third field-effect transistor produces a gradually increasing voltage at a second terminal of said third field-effect transistor, said gradually increasing voltage leveling off at a maximum voltage, for application to said NMOS driver transistor, said second circuit further comprising a fourth field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that said high drive signal produced by said pre-driver stage for said NMOS transistor applied to a first terminal of said fourth field-effect transistor rapidly produces a certain voltage at a second terminal of said fourth field-effect transistor for application to said gate of said NMOS driver transistor, said certain voltage being lower than said high drive signal voltage so as not to cause objectional ringing on said bus coupled to said NMOS driver transistor.

Claim 12

The drive circuit of claim 7 wherein said first field-effect transistor is an NMOS transistor, said second field-effect transistor is a PMOS transistor, said third field-effect transistor is a PMOS transistor, and said fourth field-effect transistor is an NMOS transistor.

Claim 13

A CMOS drive circuit for driving a logic state of a bus high or low, said drive circuit comprising: a P-channel MOS (PMOS) driver transistor and an N-channel MOS (NMOS) driver transistor coupled in series between a high state voltage source and a ground wherein said PMOS drive transistor has a source connected to said high state voltage source and said NMOS driver transistor has a drain connected to a drain of said PMOS driver transistor and a source connected to a ground, and wherein said bus is coupled to a common point of said PMOS and NMOS driver transistors; a first circuit for producing a time variant signal coupled between an NMOS pre-driver transistor in a pre-driver stage for said PMOS driver transistor and a gate of said PMOS driver transistor so that when a high digital drive signal is applied to a gate of said NMOS pre-driver transistor, charge on said gate of said PMOS driver transistor is discharged through said first circuit, said first circuit comprising a first field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that a low voltage applied to a first terminal of said field-effect transistor produces a gradually decreasing voltage at a second terminal of said first field-effect transistor, said gradually decreasing voltage leveling off at a minimum voltage, for application to said PMOS driver transistor, said first circuit further comprising a second field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that said low voltage applied to a first terminal of said second field-effect transistor rapidly produces a certain voltage at a second terminal of said second field-effect transistor for application to said gate of said PMOS driver transistor, said certain voltage being higher than said minimum voltage so as to not cause objectional ringing on said bus coupled to said PMOS driver transistor; a second circuit for producing a time variant signal coupled between a PMOS pre-driver transistor in a pre-driver stage for said NMOS driver transistor and a gate of said NMOS driver transistor so that when a low digital drive signal is applied to a gate of said PMOS pre-driver transistor, voltage is applied to said gate of said NMOS driver transistor via said second circuit, said second circuit comprising a third field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that a high voltage applied to a first terminal of said third field-effect transistor produces a gradually increasing voltage at a second terminal of said third field-effect transistor, said gradually increasing voltage leveling off at a maximum voltage, for application to said NMOS driver transistor, said second circuit further comprising a fourth field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that said high voltage applied to a first terminal of said fourth field-effect transistor rapidly produces a certain voltage at a second terminal of said fourth field-effect transistor for application to said gate of said NMOS driver transistor, said certain voltage being lower than said high voltage so as not to cause objectional ringing on said bus coupled to said NMOS driver transistor.

Claim 14

A CMOS drive circuit for driving a logic state of a bus high or low, said drive circuit comprising: a P-channel MOS (PMOS) driver transistor and an N-channel MOS (NMOS) driver transistor coupled in series between a high state voltage source and a ground wherein said PMOS drive transistor has a source connected to said high state voltage source and said NMOS driver transistor has a drain connected to a drain of said PMOS driver transistor and a source connected to a ground, and wherein said bus is coupled to a common point of said PMOS and NMOS driver transistors; a first circuit for producing a time variant signal coupled between an NMOS pre-driver transistor in a pre-driver stage for said PMOS driver transistor and a gate of said PMOS driver transistor so that when a high digital drive signal is applied to a gate of said NMOS pre-driver transistor, charge on said gate of said PMOS driver transistor is discharged through said first circuit, said first circuit comprising a first field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that a low voltage applied to a first terminal of said field-effect transistor produces a gradually decreasing voltage at a second terminal of said first field-effect transistor, said gradually decreasing voltage leveling off at a minimum voltage, for application to said PMOS driver transistor, said first circuit further comprising a second field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that said low voltage applied to a first terminal of said second field-effect transistor rapidly produces a certain voltage at a second terminal of said second field-effect transistor for application to said gate of said PMOS driver transistor, said certain voltage being higher than said minimum voltage so as to not cause objectional ringing on said bus coupled to said PMOS driver transistor; a second circuit for producing a time variant signal coupled between a PMOS pre-driver transistor in a pre-driver stage for said NMOS driver transistor and a gate of said NMOS driver transistor so that when a low digital drive signal is applied to a gate of said PMOS pre-driver transistor, voltage is applied to said gate of said NMOS driver transistor via said second circuit, said second circuit comprising a third field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that a high voltage applied to a first terminal of said third field-effect transistor produces a gradually increasing voltage at a second terminal of said third field-effect transistor, said gradually increasing voltage leveling off at a maximum voltage, for application to said NMOS driver transistor, said second circuit further comprising a fourth field-effect transistor having a gate voltage and having a channel with a width-to-length ratio such that said high voltage applied to a first terminal of said fourth field-effect transistor rapidly produces a certain voltage at a second terminal of said fourth field-effect transistor for application to said gate of said NMOS driver transistor, said certain voltage being lower than said high voltage so as not to cause objectional ringing on said bus coupled to said NMOS driver transistor.

Claim 15

The drive circuit of claim 9 wherein said first field-effect transistor is an NMOS transistor, said second field-effect transistor is a PMOS transistor, said third field-effect transistor is a PMOS transistor, and said fourth field-effect transistor is an NMOS transistor.