Solid-state relay

Claim 2

A solid-state switching device comprising: two complementary metal oxide semiconductor field-effect transistors, the first of said transistors being a P-channEl device having source and drain regions and the second of said transistors being an N-channel device having source and drain regions, the source and drain regions of different transistors being interconnected such that said transistors are connected in parallel, each of said transistors having a gate; and means for selectively shorting the substrate of one of said transistors to its source region whenever both of said transistors are rendered conducting by the simultaneous application of gating signals of appropriate amplitudes and polarities to the gates of said devices, whereby the variation of the resistance across said solid-state device, when both of said transistors are conducting is minimized with respect to variations in a signal applied to one of the interconnected source and drain regions.

Claim 3

A solid-state switching device comprising: two complementary metal oxide semiconductor field-effect transistors, the first of said transistors being a P-channEl device having source and drain regions and the second of said transistors being an N-channel device having source and drain regions, the source and drain regions of different transistors being interconnected such that said transistors are connected in parallel, each of said transistors having a gate; and means for selectively shorting the substrate of one of said transistors to its source region whenever both of said transistors are rendered conducting by the simultaneous application of gating signals of appropriate amplitudes and polarities to the gates of said devices, whereby the variation of the resistance across said solid-state device, when both of said transistors are conducting is minimized with respect to variations in a signal applied to one of the interconnected source and drain regions.

Claim 4

A solid-state switching device comprising: two complementary metal oxide semiconductor field-effect transistors, the first of said transistors being a P-channEl device having source and drain regions and the second of said transistors being an N-channel device having source and drain regions, the source and drain regions of different transistors being interconnected such that said transistors are connected in parallel, each of said transistors having a gate; and means for selectively shorting the substrate of one of said transistors to its source region whenever both of said transistors are rendered conducting by the simultaneous application of gating signals of appropriate amplitudes and polarities to the gates of said devices, whereby the variation of the resistance across said solid-state device, when both of said transistors are conducting is minimized with respect to variations in a signal applied to one of the interconnected source and drain regions.

Claim 5

The switching device as recited in claim 1 wherein the substrate of one of said transistors is formed in the substrate of the other of said transistors, the substrate formed in the substrate of the other transistor being that substrate which is connected to its own source region by said means, whereby the sensitivity to input signals of the device associated with the substrate formed in the substrate of said other transistor is diminished.

Claim 6

The switching device as recited in claim 2 wherein said means includes an additional solid-state switching device serially connected between said substrate formed in a substrate and the source region associated with said substrate formed in a substrate, said switching device being rendered conductive by the presence of one of said gating signals so as to connect the substrate formed in a substrate to the source region associated therewith.

Claim 7

The switching device recited in claim 3 wherein said additional switching device is a metal oxide semiconductor field-effect transistor of the same type as that transistor into whose substrate a substrate is formed, the gate of said additional switching device and that of the transistor into whose substrate a substrate is formed being interconnected.

Claim 8

A solid-state switching device comprising: a metal oxide semiconductor field-effect transistor having a source region adapted to receive an input signal, a drain region, and a gate adapted to receive a gating signal which renders said transistor conducting such that said input signal is available at said drain region whenever said transistor is rendered conductive; and means for selectively shorting the substrate of said transistor to said source region whenever said transistor is rendered conducting, whereby the change in resistance across said transistor with respect to changes in the amplitude of said input signal is minimized such that distortion of said input signal at said drain region is also minimized.

Claim 9

A solid-state switching device comprising: a metal oxide semiconductor field-effect transistor having a source region adapted to receive an input signal, a drain region, and a gate adapted to receive a gating signal which renders said transistor conducting such that said input signal is available at said drain region whenever said transistor is rendered conductive; and means for selectively shorting the substrate of said transistor to said source region whenever said transistor is rendered conducting, whereby the change in resistance across said transistor with respect to changes in the amplitude of said input signal is minimized such that distortion of said input signal at said drain region is also minimized.

Claim 10

The solid-state switching device is recited in claim 5 wherein said means includes an additional solid-state switching device coupled between the substrate of said transistor and said source region, said additional switching means being rendered conductive simultaneously with said transistor.

Claim 11

The solid-state switching device as recited in claim 6 wherein said additional solid-state switching device is a metal oxide semiconductor field-effect transistor.

Claim 12

The solid-state switching device as recited in claim 7 wherein said additional metal oxide semiconductor is of a type opposite to that of said first mentioned field-effect transistor, said additional solid-state switching device being rendered conductive simultaneously with said first mentioned transistor.

Claim 13

A solid-state switching device comprising: a block of semiconductive material of a first conductivity type having a top surface; a tub of semiconductive material of an opposite conductivity type to that of said block, within said block and extending downwardly from said top surface in one region of said block, said tub having a surface coplanar with that of said block; first source and drain regions extending into said tub from a top surface thereof said first source and drain regions being of said first conductivity type; a first gate layer on the surface of said tub and overlying portions of said first source and drain regions, said first gate layer being of an insulating material; second source and drain regions extending into said block from the top surface thereof and spaced from said tub, said second source and drain regions being of said opposite conductivity type; a second gate layer on the top surface of said block and overlying portions of said second source and drain regions, said second gate layer being formed from an insulating material; third source and drain regions of said opposite conductivity type extending into said block from the top surface thereof; a third gate layer overlying portions of said third source and drain regions; patterned metallization over the top surface of said device, said metallization forming contacts to said source and drain regions and said gate layers, the impurity concentration in said block, said tub and each of said source and drain regions being such that the devices formed by said structures are enhancement mode devices; means for connecting said first source region to said second drain region, said means also forming an input terminal for said solid-state switch means for connecting said second source region to said first drain region, said last mentioned means also forming an output terminal for said solid-state switch; means for connecting said third gate layer to said second gate layer; means for connecting said third drain region to said output terminal; means for connecting said third source region to said tub; isolating means between said second source and drain regions and said first and third source and drain regions; means adapted to receive a biasing voltage for contacting said block; and means for applying appropriate polarity gating signals to said first and second gate layers to render said switching device conductive whereby whenever said gating signals and bias voltage are applied, any input signal at said input terminal will be transmitted through said switching device to said output terminal with a minimum of distortion.

Claim 14

A solid-state switching device comprising: a block of semiconductive material of a first conductivity type having a top surface; a tub of semiconductive material of an opposite conductivity type to that of said block, within said block and extending downwardly from said top surface in one region of said block, said tub having a surface coplanar with that of said block; first source and drain regions extending into said tub from a top surface thereof said first source and drain regions being of said first conductivity type; a first gate layer on the surface of said tub and overlying portions of said first source and drain regions, said first gate layer being of an insulating material; second source and drain regions extending into said block from the top surface thereof and spaced from said tub, said second source and drain regions being of said opposite conductivity type; a second gate layer on the top surface of said block and overlying portions of said second source and drain regions, said second gate layer being formed from an insulating material; third source and drain regions of said opposite conductivity type extending into said block from the top surface thereof; a third gate layer overlying portions of said third source and drain regions; patterned metallization over the top surface of said device, said metallization forming contacts to said source and drain regions and said gate layers, the impurity concentration in said block, said tub and each of said source and drain regions being such that the devices formed by said structures are enhancement mode devices; means for connecting said first source region to said second drain region, said means also forming an input terminal for said solid-state switch means for connecting said second source region to said first drain region, said last mentioned means also forming an output terminal for said solid-state switch; means for connecting said third gate layer to said second gate layer; means for connecting said third drain region to said output terminal; means for connecting said third source region to said tub; isolating means between said second source and drain regions and said first and third source and drain regions; means adapted to receive a biasing voltage for contacting said block; and means for applying appropriate polarity gating signals to said first and second gate layers to render said switching device conductive whereby whenever said gating signals and bias voltage are applied, any input signal at said input terminal will be transmitted through said switching device to said output terminal with a minimum of distortion.

Claim 15

The switching device as recited in claim 9 wherein said connecting means are provided by said patterned metallization.

Claim 16

A solid-state switching device comprising: a block of semiconductive material of a first conductivity type having a top surface; a tub of semiconductive material of an opposite conductivity type to that of said block, within said block and extending downwardly from said top surface in one region of said block, said tub having a surface coplanar with that of said block; first source and drain regions extending into said tub from a top surface thereof, said first source and drain regions being of said first conductivity type; a first gate layer on the surface of said tub and overlying portions of said first source and drain regions, said first gate layer being of an insulating material; second source and drain regions extending into said block from the top surface thereof and spaced from said tub, said second source and drain regions being of said opposite conductivity type; a second gate layer on the top surface of said block and overlying portions of said second source and drain regions, said second gate layer being formed from an insulating material; third source and drain regions of said opposite conductivity type, said third drain region extending into said block from the top surface thereof, said third source region extending into said tub from the top surface thereof; a third gate layer overlying portions of said third source and drain regions; patterned metallization over the top surface of said device, said metallization forming contacts to said source and drain regions and said gate layers, the impurity concentration in said block, said tub and eacH of said source and drain regions being such that the devices formed by said structures are enhancement mode devices; means for connecting said first source region to said second drain region, said means also forming an input terminal for said solid-state switch; means for connecting said second source region to said first drain region, said means also forming an output terminal for said solid-state switch; means for connecting said third gate layer to said second gate layer; means for connecting said third drain region to said output terminal; isolating means between said second source and drain regions and said first and third source and drain regions; means adapted to receive a biasing voltage for contacting said block; and means for applying appropriate polarity gating signals to said first and second gate layers to render said switching device conductive whereby whenever said gating signals and bias voltage are applied, any input signal at said input terminal will be transmitted through said switching device to said output terminal with a minimum of distortion.

Claim 17

A solid-state switching device comprising: a block of semiconductive material of a first conductivity type having a top surface; a tub of semiconductive material of an opposite conductivity type to that of said block, within said block and extending downwardly from said top surface in one region of said block, said tub having a surface coplanar with that of said block; first source and drain regions extending into said tub from a top surface thereof, said first source and drain regions being of said first conductivity type; a first gate layer on the surface of said tub and overlying portions of said first source and drain regions, said first gate layer being of an insulating material; second source and drain regions extending into said block from the top surface thereof and spaced from said tub, said second source and drain regions being of said opposite conductivity type; a second gate layer on the top surface of said block and overlying portions of said second source and drain regions, said second gate layer being formed from an insulating material; third source and drain regions of said opposite conductivity type, said third drain region extending into said block from the top surface thereof, said third source region extending into said tub from the top surface thereof; a third gate layer overlying portions of said third source and drain regions; patterned metallization over the top surface of said device, said metallization forming contacts to said source and drain regions and said gate layers, the impurity concentration in said block, said tub and eacH of said source and drain regions being such that the devices formed by said structures are enhancement mode devices; means for connecting said first source region to said second drain region, said means also forming an input terminal for said solid-state switch; means for connecting said second source region to said first drain region, said means also forming an output terminal for said solid-state switch; means for connecting said third gate layer to said second gate layer; means for connecting said third drain region to said output terminal; isolating means between said second source and drain regions and said first and third source and drain regions; means adapted to receive a biasing voltage for contacting said block; and means for applying appropriate polarity gating signals to said first and second gate layers to render said switching device conductive whereby whenever said gating signals and bias voltage are applied, any input signal at said input terminal will be transmitted through said switching device to said output terminal with a minimum of distortion.

Claim 18

A solid-state switching device comprising: a block of semiconductive material of a first conductivity type having a top surface; a tub of semiconductive material of an opposite conductivity type to that of said block, within said block and extending downwardly from said top surface in one region of said block, said tub having a surface co-planar with that of said block; first source and drain regions extending into said tub from a top surface thereof, said first source and drain regions being of said first conductivity type; a first gate layer on the surface of said tub and overlying portions of said first source and drain regions, said first gate layer being of an insulating material; second source and drain regions extending into said block from the top surface thereof and spaced from said tub, said second source and drain regions being of said opposite conductivity type; a second gate layer on the top surface of said block and overlying portions of said second source and drain regions, said second gate layer being formed from an insulating material; third source and drain regions of said opposite conductivity type extending into said block from the top surface thereof; a third gate layer overlying portions of said third source and drain regions; patterned metalization over the top surface of said device, said metalization forming contacts to said source and drain regions and said gate layers, the impurity concentration in said block, said tub and each of said source and drain regions being such that the devices formed by said structures are enhancement mode devices; means for connecting said first source region to said second drain region, said means also forming an input terminal for said solid-state switch; means for connecting said second source region to said first drain region, said last-mentioned means also forming an output terminal for said solid-state switch; means for connecting said third gate layer to said second gate layer; means for connecting said third drain region to said input terminal; means for connecting said third source region to said tub; isolating means between said second source and drain regions and said first and third source and drain regions; means adapted to receive a biasing voltage for contacting said block; and means for applying appropriate polarity gating signals to said first and second gate layers to render said switching device conductive whereby whenever said gating signals and bias voltage are applied, any input signal at said input terminal will be transmitted through said switching device to said output terminal with a minimum of distortion.

Claim 19

A solid-state switching device comprising: a block of semiconductive material of a first conductivity type having a top surface; a tub of semiconductive material of an opposite conductivity type to that of said block, within said block and extending downwardly from said top surface in one region of said block, said tub having a surface co-planar with that of said block; first source and drain regions extending into said tub from a top surface thereof, said first source and drain regions being of said first conductivity type; a first gate layer on the surface of said tub and overlying portions of said first source and drain regions, said first gate layer being of an insulating material; second source and drain regions extending into said block from the top surface thereof and spaced from said tub, said second source and drain regions being of said opposite conductivity type; a second gate layer on the top surface of said block and overlying portions of said second source and drain regions, said second gate layer being formed from an insulating material; third source and drain regions of said opposite conductivity type extending into said block from the top surface thereof; a third gate layer overlying portions of said third source and drain regions; patterned metalization over the top surface of said device, said metalization forming contacts to said source and drain regions and said gate layers, the impurity concentration in said block, said tub and each of said source and drain regions being such that the devices formed by said structures are enhancement mode devices; means for connecting said first source region to said second drain region, said means also forming an input terminal for said solid-state switch; means for connecting said second source region to said first drain region, said last-mentioned means also forming an output terminal for said solid-state switch; means for connecting said third gate layer to said second gate layer; means for connecting said third drain region to said input terminal; means for connecting said third source region to said tub; isolating means between said second source and drain regions and said first and third source and drain regions; means adapted to receive a biasing voltage for contacting said block; and means for applying appropriate polarity gating signals to said first and second gate layers to render said switching device conductive whereby whenever said gating signals and bias voltage are applied, any input signal at said input terminal will be transmitted through said switching device to said output terminal with a minimum of distortion.