US4725747A
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Integrated circuit distributed geometry to reduce switching noise
Assignee: Texas Instruments Inc
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Filing: 1986-08-29
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Granted: 1988-02-16
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Expires: 2006-08-29
Abstract
Abstract A complimentary output pair (10) having a P-channel transistor (12) and an N-channel transistor (14) prevents output voltage spikes due to rapid changes in current with respect to time at the V cc power supply and ground (32) nodes by using a "graded turn-on." Both the P-channel transistor (12) and the N-channel (14) utilize a serpentine polysilicon gate (16), (24), in order to sequentially turn on the sub-transistors in response to a changing input. Pull-up (36) and pull-down (40) transistors are used to turn the sub-transistors (21a-j, 29a-f) off simultaneously.
Inventors
- 👤 Dale P. Stein
- 👤 Sam M. Weaver
- 👤 James C. Spurlin
- 👤 Steven E. Marum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:39
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K17/164; H03K17/12; H03K17/122
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
104 words
A transistor comprising: a substrate having a first semiconductor region comprised of semiconductor surface areas forming a plurality of transistor regions; and an elongated gate having a predetermined resistance and being disposed adjacent said semiconductor surface areas in a series configuration such that a gate signal applied to one end region of said gate propagates along the length of said gate in a predetermined time interval; the propagation of said gate signal along said gate causing sequential conduction of ones of said transistor regions until all of said transistor regions are conducting said sequential conduction reducing the generation of output noise by said transistor.
Claim 2
Dependent Claim
104 words
A transistor comprising: a substrate having a first semiconductor region comprised of semiconductor surface areas forming a plurality of transistor regions; and an elongated gate having a predetermined resistance and being disposed adjacent said semiconductor surface areas in a series configuration such that a gate signal applied to one end region of said gate propagates along the length of said gate in a predetermined time interval; the propagation of said gate signal along said gate causing sequential conduction of ones of said transistor regions until all of said transistor regions are conducting said sequential conduction reducing the generation of output noise by said transistor.
Claim 3
Dependent Claim
21 words
The transistor of claim 1 wherein said elongated gate is configured in a continuous serpentine configuration over said semiconductor surface areas.
Claim 4
Dependent Claim
42 words
The transistor of claim 1 and further comprising a second semiconductor region separate from said semiconductor surface areas, said elongated gate also disposed adjacent said second semiconductor region such that the resistance of said elongated gate is increased by its increased length.
Claim 5
Dependent Claim
46 words
The transistor of claim 1, wherein said elongated gate is formed of polysilicon with elongated regions extending parallel to sources and drains of said transistor and joined at end regions by short regions perpendicular to said sources and drains to form a single continuous serially-connected gate.
Claim 6
Dependent Claim
77 words
The transistor of claim 1 wherein said transistor regions have varying geometric areas; at least one of said transistor regions being located at a point along the path of propagation of said gate signal and having a greater geometric area than another transistor region located at a point earlier along said conducting path; and said gate extending over areas outside said another transistor in order to provide sufficient gate length to create desirable input signal propagation delay.
Claim 7
Dependent Claim
78 words
The transistor of claim 3 wherein said transistor regions have varying geometric areas; at least one of said transistor regions being located at a point along the path of propagation of said gate signal and having a greater geometric area than another transistor region located at a point earlier along said conducting path; and said gate extending over areas outside said another transistor region in order to provide sufficient gate length to create desirable input signal propagation delay.
Claim 8
Dependent Claim
49 words
The transistor of claim 6, wherein said transistor further comprises a plurality of turn-off transistors, said turn-off transistors having drains connected to said elongated gate such that all said transistor regions are substantially simultaneously rendered non-conductive in response to a signal applied at one end of said elongated gate.
Claim 9
Dependent Claim
78 words
A transistor circuit comprising: a body of semiconductor material; a plurality of active semiconductor regions associated with said body to form alternating transistor sources and drains; an elongated conductive gate disposed adjacent said active semiconductor regions to form a plurality of interconnected transistors, said gate having a resistance and configured in a continuous serpentine manner such that a gate signal applied to one end thereof propagates serially along said gate to sequentially render ones of said transistors conductive.
Claim 10
Dependent Claim
78 words
A transistor circuit comprising: a body of semiconductor material; a plurality of active semiconductor regions associated with said body to form alternating transistor sources and drains; an elongated conductive gate disposed adjacent said active semiconductor regions to form a plurality of interconnected transistors, said gate having a resistance and configured in a continuous serpentine manner such that a gate signal applied to one end thereof propagates serially along said gate to sequentially render ones of said transistors conductive.
Claim 11
Dependent Claim
152 words
A transistor circuit comprising: a body of semiconductor material; a plurality of active semiconductor regions associated with said body to form alternating transistor sources and drains; an elongated conductive gate disposed adjacent said active semiconductor regions to form a plurality of interconnected transistors, said gate having a resistance and configured in a continuous serpentine manner such that a gate signal applied at one end thereof propagates serially along said gate to sequentially render ones of said transistors conductive; a second plurality of active semiconductor regions associated with said body to form alternating sources and drains; and a second elongated conductive gate disposed adjacent to said second plurality of semiconductor regions to form a second plurality of interconnected transistors, said second elongated gate having resistance and configured in a serpentine manner such that a gate signal applied at one end thereof propagates along said gate to sequentially render ones of said transistors conductive.
Claim 12
Dependent Claim
152 words
A transistor circuit comprising: a body of semiconductor material; a plurality of active semiconductor regions associated with said body to form alternating transistor sources and drains; an elongated conductive gate disposed adjacent said active semiconductor regions to form a plurality of interconnected transistors, said gate having a resistance and configured in a continuous serpentine manner such that a gate signal applied at one end thereof propagates serially along said gate to sequentially render ones of said transistors conductive; a second plurality of active semiconductor regions associated with said body to form alternating sources and drains; and a second elongated conductive gate disposed adjacent to said second plurality of semiconductor regions to form a second plurality of interconnected transistors, said second elongated gate having resistance and configured in a serpentine manner such that a gate signal applied at one end thereof propagates along said gate to sequentially render ones of said transistors conductive.
Claim 13
Dependent Claim
34 words
The transistor circuit of claim 9 wherein said drains of said first plurality of active semiconductor regions and said drains of said second plurality of active semiconductor regions are connected to form an output.
Claim 14
Dependent Claim
42 words
The transistor circuit of claim 9 wherein said sources of said first plurality of active semiconductor regions are connected to the power supply of the transistor circuit and the sources of said second plurality of active semiconductor regions are connected to ground.
Claim 15
Dependent Claim
18 words
The transistor circuit of claim 11 wherein an input is connected to said first and second elongated gates.
Claim 16
Dependent Claim
21 words
The transistor circuit of claim 12 wherein an invertor is placed between said input and said first and second elongated gates.
Claim 17
Dependent Claim
163 words
The transistor circuit of claim 12 wherein: said input is connected to the gates of a first plurality of turn-off transistors and to a second plurality of turn-off transistors; the drains of said first set of turn-off transistors connected to successive positions along said first elongated gate, and the sources of said first set of turn-off transistors connected to the power supply of said transistor circuit; the drains of said second set of turn-off transistors connected to successive positions along said second elongated gate and the sources of said second set of turn-off transistors connected to the circuit ground; said first plurality of turn-off transistors disposed to apply the power supply voltage to said first elongated gate when a logical high signal is present at one end of said first elongated gate; and said second plurality of turn-off transistors disposed to apply ground to said second elongated gate when a logical low signal is present at one end of said second elongated gate.
Claim 18
Dependent Claim
34 words
The transistor circuit of claim 9 wherein said second elongated gate has an extended region disposed beyond said second plurality of interconnected transistors, such that the resistance of said second elongated gate is increased.
Claim 19
Dependent Claim
34 words
The transistor circuit of claim 9 wherein said second extended region of elongated gate is disposed adjacent a third plurality of semiconductor regions such that the capacitance of said second elongated gate is increased.
Claim 20
Dependent Claim
108 words
A CMOS transistor circuit having low output noise comprising: a semiconductor body; a P-channel transistor formed by a plurality of active semiconductor regions associated with said body; a N-channel transistor formed by a plurality of active semiconductor regions associated with said body; said P-channel and said N-channel transistors interconnected to generate an output signal in response to an input signal; each of said transistors including a series serpentine conductive gate disposed adjacent said respective active semiconductor regions and coupled to receive the input signal, said conductive gate having a predetermined resistance such that said input signal propagates along the length of said gate during a predetermined time period.
Claim 21
Dependent Claim
108 words
A CMOS transistor circuit having low output noise comprising: a semiconductor body; a P-channel transistor formed by a plurality of active semiconductor regions associated with said body; a N-channel transistor formed by a plurality of active semiconductor regions associated with said body; said P-channel and said N-channel transistors interconnected to generate an output signal in response to an input signal; each of said transistors including a series serpentine conductive gate disposed adjacent said respective active semiconductor regions and coupled to receive the input signal, said conductive gate having a predetermined resistance such that said input signal propagates along the length of said gate during a predetermined time period.
Claim 22
Independent Claim
83 words
A method of reducing noise in the output signal of semiconductor transistor which includes a plurality of transistor regions, comprising: applying an input signal to a first one of said transistor regions to render said one transistor region conductive; propagating said input signal sequentially along a serpentine gate such that the remainder of said transistor regions are sequentially rendered conductive; and generating an output signal during the sequential conduction of said transistor regions in order to reduce noise spikes in said output signal.
Claim 23
Independent Claim
83 words
A method of reducing noise in the output signal of semiconductor transistor which includes a plurality of transistor regions, comprising: applying an input signal to a first one of said transistor regions to render said one transistor region conductive; propagating said input signal sequentially along a serpentine gate such that the remainder of said transistor regions are sequentially rendered conductive; and generating an output signal during the sequential conduction of said transistor regions in order to reduce noise spikes in said output signal.
Claim 24
Dependent Claim
34 words
The method of claim 18, and further comprising applying a second input signal to all of said transistor regions substantially simultaneously after generating said output signal in order to render said transistor regions non-conductive.
Claim 25
Dependent Claim
29 words
The method of claim 18 and further comprising adding delay to the propagation of said input signal after said input signal has rendered ones of said transistor regions conductive.
Claim 26
Dependent Claim
26 words
The method of claim 19 wherein said delay is added by propagating said input signal adjacent to a semiconductor region in order to provide capacitive delay.
Claim 27
Dependent Claim
35 words
The method of claim 18, and further comprising fabricating transistor regions having lesser and greater areas such that transistor regions having lesser areas are rendered conductive before transistor regions having greater areas are rendered conductive.
References Cited (Backward Citations)
US4152717A
Cited
US4462041A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |