US5331228A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output driver circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1992-07-31
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Granted: 1994-07-19
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Expires: 2012-07-31
Abstract
Abstract An output driver circuit includes a sense amplifier coupled to a first inverter and a second inverter. The first and second inverters drive a first and second chain of logic gates, respectively. A p-channel output transistor is coupled to the output of the first chain of logic gates, and an n-channel output transistor is coupled to the output of the second chain of logic gates. The transistors in the first and second inverters are selected so that the first inverter and the second inverter have complementary preferential output states. The first and second inverters generate their preferential output state in response to a selected intermediate output voltage range from the sense amplifier to turn off both the n-channel transistor and the p-channel transistor. This causes the n-channel and p-channel output transistors to both turn off when the sense amplifier generates the intermediate voltage during an equilibrate period.
Inventors
- 👤 James Brady
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:40
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
190 words
An output driver circuit, comprising: a sense amplifier having an output; a first inverter and a second inverter coupled to said sense amplifier, each inverter having one-channel transistor and one p-channel transistor, wherein said first inverter and said second inverter are utilized to drive a first and second chain of logic gates respectively, and wherein the transistors in the first inverter and the second inverter are selected so that said first inverter and said second inverter have complementary preferential output states, said first inverter consisting of an additional p-channel transistor in series with its p-channel transistor and said second inverter consisting of an additional n-channel transistor in series with its n-channel transistor, wherein the additional transistors force the inverters to the preferential output states when receiving a gating signal; and a p-channel output transistor coupled to said first chain of logic gates and an n-channel output transistor coupled to said second chain of logic gates, wherein the first and second inverters generate their preferential output states in response to an intermediate voltage range from the sense amplifier to turn off both the n-channel output transistor and the p-channel output transistor.
Claim 2
Dependent Claim
190 words
An output driver circuit, comprising: a sense amplifier having an output; a first inverter and a second inverter coupled to said sense amplifier, each inverter having one-channel transistor and one p-channel transistor, wherein said first inverter and said second inverter are utilized to drive a first and second chain of logic gates respectively, and wherein the transistors in the first inverter and the second inverter are selected so that said first inverter and said second inverter have complementary preferential output states, said first inverter consisting of an additional p-channel transistor in series with its p-channel transistor and said second inverter consisting of an additional n-channel transistor in series with its n-channel transistor, wherein the additional transistors force the inverters to the preferential output states when receiving a gating signal; and a p-channel output transistor coupled to said first chain of logic gates and an n-channel output transistor coupled to said second chain of logic gates, wherein the first and second inverters generate their preferential output states in response to an intermediate voltage range from the sense amplifier to turn off both the n-channel output transistor and the p-channel output transistor.
Claim 3
Dependent Claim
48 words
The circuit of claim 1, wherein said sense amplifier reads a memory and said gating signal is derived from an equilibrate signal form the memory, and wherein the gating signal drives the first additional transistor in the first inverter and the second additional transistor in the second inverter.
Claim 4
Dependent Claim
29 words
The circuit of claim 2, wherein said equilibrate signal is utilized to set a data line and a complementary data line within the memory to an equivalent voltage level.
Claim 5
Dependent Claim
33 words
The circuit of claim 2, wherein the data line and the complementary data line within the memory are set to the equivalent voltage level when said equilibrate signal comprises a low voltage level.
Claim 6
Dependent Claim
36 words
The circuit of claim 1, wherein the sizes of the n-channel and the p-channel transistors in the first and second inverters are selected so that the first and second inverters have the complementary preferential output state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-18 | 1998-01-17 | 1998-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-18 | 2002-01-17 | 2002-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-18 | 2006-01-17 | 2006-07-19 | $7700.00 | Window Closed / Lapsed |