US4797579A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS VLSI output driver with controlled rise and fall times
Assignee: Raytheon Co
•
Filing: 1987-07-27
•
Granted: 1989-01-10
•
Expires: 2007-07-27
Abstract
Abstract A CMOS output driver having precise control of rise and fall times of signals generated from the output driver on a VLSI semiconductor chip. Two time-dependent voltage generators provide a separate ramp signal to each one of the gates of a CMOS inverter circuit. The ramp signal characteristics of each voltage generator are determined by the combination of a controlled current source charging a known capacitance.
Inventors
- 👤 Edward T. Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:22
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/94; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
103 words
A CMOS output circuit for producing an output signal comprising: an input signal applied to said output circuit; first means coupled to receive said input signal for generating an approximately linear decreasing signal for control of said output signal rise time; second means coupled to receive said input signal for generating an approximately linear increasing signal for control of said output signal fall time; and means, free of any output feedback connections, for producing said output signal having a first input coupled to an output of said first control means and a second input coupled to an output of said second control means.
Claim 2
Dependent Claim
103 words
A CMOS output circuit for producing an output signal comprising: an input signal applied to said output circuit; first means coupled to receive said input signal for generating an approximately linear decreasing signal for control of said output signal rise time; second means coupled to receive said input signal for generating an approximately linear increasing signal for control of said output signal fall time; and means, free of any output feedback connections, for producing said output signal having a first input coupled to an output of said first control means and a second input coupled to an output of said second control means.
Claim 3
Dependent Claim
23 words
The CMOS output circuit as recited in claim 1 wherein: said first control means comprises an unbalanced inverter coupled to a capacitive means.
Claim 4
Dependent Claim
23 words
The CMOS output circuit as recited in claim 1 wherein: said second control means comprises an unbalanced inverter coupled to a capacitive means.
Claim 5
Dependent Claim
22 words
The CMOS output circuit as recited in claim 1 wherein: said output signal producing means comprises a pair of complementary MOS transistors.
Claim 6
Dependent Claim
129 words
A driver circuit having an output signal with controlled rise and fall times comprising: an input signal applied to said driver circuit; a buffer circuit coupled to receive said input signal for providing drive capability for said input signal; a first voltage generator means coupled to an output of said buffer circuit for generating an approximately linear decreasing signal for signal rise time; a second voltage generator means coupled to said output of said buffer circuit for generating an approximately linear control of said output signal fall time; and complementary MOS transistors, free of any output feedback connections, having a first input coupled to an output of said first voltage generator and a second input coupled to an output of said second voltage generator for producing said output signal.
Claim 7
Dependent Claim
129 words
A driver circuit having an output signal with controlled rise and fall times comprising: an input signal applied to said driver circuit; a buffer circuit coupled to receive said input signal for providing drive capability for said input signal; a first voltage generator means coupled to an output of said buffer circuit for generating an approximately linear decreasing signal for signal rise time; a second voltage generator means coupled to said output of said buffer circuit for generating an approximately linear control of said output signal fall time; and complementary MOS transistors, free of any output feedback connections, having a first input coupled to an output of said first voltage generator and a second input coupled to an output of said second voltage generator for producing said output signal.
Claim 8
Dependent Claim
31 words
The driver circuit as recited in claim 5 wherein: said first voltage generator means comprises a controlled source of current charging a capacitive means for controlling said output signal rise time.
Claim 9
Dependent Claim
31 words
The driver circuit as recited in claim 5 wherein: said second voltage generator means compriess a controlled source of current charging a cpacitive means for controlling said output signal fall time.
Claim 10
Dependent Claim
21 words
The drive circuit as recited in claim 5 wherein: said complementary MOS transistors comprise a P-channel transistor and an N-channel transistor.
Claim 11
Independent Claim
126 words
The method of controlling the rise and fall tims of an output signal from a VLSI chip output circuit comprsiing the steps of: providing an input signal to said output circuit; generating an approximately linear decreasing signal in response to one edge of said input signal with a first voltage generator means; generating an approximately linear increasing signal in response to the other edge of said input signal with a second voltage generator means; and producing said output signal having controlled rise and fall times with a pair of complementary MOS transistors, free of an output feedback connections, having a first input coupled to an output of said first voltage generator means and a second input coupled to an output of said second voltage generator means.
Claim 12
Independent Claim
126 words
The method of controlling the rise and fall tims of an output signal from a VLSI chip output circuit comprsiing the steps of: providing an input signal to said output circuit; generating an approximately linear decreasing signal in response to one edge of said input signal with a first voltage generator means; generating an approximately linear increasing signal in response to the other edge of said input signal with a second voltage generator means; and producing said output signal having controlled rise and fall times with a pair of complementary MOS transistors, free of an output feedback connections, having a first input coupled to an output of said first voltage generator means and a second input coupled to an output of said second voltage generator means.
Claim 13
Dependent Claim
55 words
The method as recited in claim 9 further comprising the steps of: adjusting the slope of said output signal rise time by selecting a saturation current for said first voltage generator means; and adjusting the slope of said output signal rise time by selecting a capacitance at the output of said first voltage generator means.
Claim 14
Dependent Claim
54 words
The method as recited in claim 9 further comprising the steps of: adjusting the slope of said output signal fall time by selecting a saturation current for said second voltage generator means; and adjusting the slope of said output signal fall time by selecting a capacitance at the output of said second voltage generator.
References Cited (Backward Citations)
US4103188A
Cited
US4518873A
Cited
US4661928A
Cited
US4727266A
Cited
US4567378A
Cited
US4719369A
Cited
US4622482A
Cited
US4725747A
Cited
US4724340A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-10 | 1992-07-11 | 1993-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-10 | 1996-07-11 | 1997-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-10 | 2000-07-11 | 2001-01-10 | $7700.00 | Window Closed / Lapsed |