Buffer circuit for driving a C-MOS inverter

Claim 2

A buffer circuit, operatively connected to receive an input signal, for driving a C-MOS inverter having first and second transistors, said buffer circuit comprising: first and second inverters operatively connected between a power supply line and ground and operatively connected to receive the input signal, for inverting the input signal and for providing an output signal for driving the first and second transistors in the C-MOS inverter, said first inverter having a first output terminal operatively connected to the first transistor and comprising at least one first switching delay transistor operatively connected in series between the power supply line and ground, said second inverter having a second output terminal operatively connected to the second transistor and comprising at least one second switching delay transistor operatively connected in series between the power supply line and ground; delay means, operatively connected to said first and second inverters and operatively connected to receive the input signal, for providing a delay signal having a predetermined delay time with respect to the input signal; and said first and second switching delay transistors receiving the delay signal from said delay means, having a predetermined delay time with respect to the input signal to prevent simultaneous conduction of current through the first and second transistors in the C-MOS inverter.

Claim 3

A buffer circuit as set forth in claim 1: wherein the first and second transistors in the C-MOS inverter comprise a p-MOS transistor and an n-MOS transistor, respectively; wherein said first inverter further comprises at least two more transistors, operatively connected in series with each other and said first switching delay transistor and operatively connected to said p-MOS transistor, for driving said p-MOS transistor; wherein said second inverter further comprises at least two more transistors, operatively connected in series with each other and said second switching delay transistor and operatively connected to said n-MOS transistor, for driving said n-MOS transistor.

Claim 4

A buffer circuit as set forth in claim 2: wherein said one of at least two more transistors of said first inverter comprises a first p-MOS transistor operatively connected to the power supply line and wherein the other one of said at least two more transistors comprises a first n-MOS transistor operatively connected in series with said first p-MOS transistor, the connection of said first p-MOS transistor and said first n-MOS transistor forming a first connection point therebetween; wherein said first output terminal is operatively connected to said first connection point; wherein the first switching delay transistor comprises a second n-MOS transistor operatively connected in series between said first n-MOS transistor and ground; wherein said one of at least two more transistors of said second inverter comprises a second p-MOS transistor operatively connected to the power supply and wherein the other one of said at least two more transistors of said second inverter comprises a third n-MOS transistor operatively connected to ground; wherein the second switching delay transistor of said second inverter comprises a third p-MOS transistor operatively connected in series between said second p-MOS transistor and said third n-MOS transistor, the connection of said third p-MOS transistor and said third n-MOS transistor forming a second connection point therebetween; and wherein said second output terminal is operatively connected to said second connection point.

Claim 5

A buffer circuit as set forth in claim 2: wherein said one of at least two more transistors of said first inverter comprises a first p-MOS transistor operatively connected to the power supply line, wherein the first switching delay transistor of said first inverter comprises a first n-MOS transistor operatively connected to ground, and wherein the other of said at least two more transistors comprises a second n-MOS transistor operatively connected in series between said first p-MOS transistor and said first n-MOS transistor, the connection of said first p-MOS transistor and said second n-MOS transistor forming a first connection point therebetween; wherein said first output terminal is operatively connected to said first connection point; wherein said one of at least two more transistors of said second inverter comprises a third n-MOS transistor operatively connected to ground, wherein the second switching delay transistor of said second inverter comprises a second p-MOS transistor operatively connected in series with said third n-MOS transistor, and wherein the other of said at least two more transistors comprises a third p-MOS transistor operatively connected in series between the power supply line and said second p-MOS transistor, the connection of said second p-MOS transistor and said third n-MOS transistor forming a second connection point therebetween; and wherein said second output terminal is operatively connected to said second connection point.

Claim 6

A buffer circuit as set forth in claim 2: wherein said first switching delay transistor and said at least two more transistors of said first inverter comprise n-MOS transistors operatively connected in series between the power supply and ground, wherein a first one of said at least two transistors is operatively connected to receive an inverted signal of the input signal, wherein a second one of said at least two transistors is operatively connected to receive the input signal, and wherein said first switching delay transistor is operatively connected to receive the delay signal, the connection between said first and second transistors forming a first connection point therebetween, and wherein said first output terminal is operatively connected to said first connection point; and wherein said second switching delay transistor and said at least two more transistors of said second inverter comprise n-MOS transistors operatively connected in series between the power supply and ground, wherein a first one of said at least two transistors of said second inverter is operatively connected to receive the inverted input signal, wherein said second switching delay of said second inverter is operatively connected to receive an inverted signal of the delay signal, and wherein a second one of said at least two transistors of said second inverter is operatively connected to receive the input signal, the connection between said second and third transistors forming a second connection point therebetween, and wherein said second output terminal is operatively connected to said second connection point.

Claim 7

A buffer circuit, having an input terminal operatively connected to receive an input signal and having a output for driving a C-MOS inverter circuit having a first p-MOS transistor and a first n-MOS transistor operatively connected in series between a power supply and ground and having an output terminal, said buffer circuit comprising: a first inverter circuit, having an output node operatively connected to the first p-MOS transistor and having an input node operatively connected to the input terminal, for receiving the input signal and for driving the first p-MOS transistor; a second inverter circuit, having an output node operatively connected to the first n-MOS transistor and having an input node operatively connected to the input terminal, for receiving the input signal and for driving the first n-MOS transistor; and a delay circuit, operatively connected between the input terminal and said first and second inverters, for receiving the input signal and generating a delay signal having a predetermined delay time.

Claim 8

A buffer circuit, having an input terminal operatively connected to receive an input signal and having a output for driving a C-MOS inverter circuit having a first p-MOS transistor and a first n-MOS transistor operatively connected in series between a power supply and ground and having an output terminal, said buffer circuit comprising: a first inverter circuit, having an output node operatively connected to the first p-MOS transistor and having an input node operatively connected to the input terminal, for receiving the input signal and for driving the first p-MOS transistor; a second inverter circuit, having an output node operatively connected to the first n-MOS transistor and having an input node operatively connected to the input terminal, for receiving the input signal and for driving the first n-MOS transistor; and a delay circuit, operatively connected between the input terminal and said first and second inverters, for receiving the input signal and generating a delay signal having a predetermined delay time.

Claim 9

A buffer circuit as set forth in claim 6, wherein said first inverter circuit comprises: a second p-MOS transistor operatively connected to the power supply and the input terminal; a second n-MOS transistor, operatively connected to the input terminal and operatively connected in series with said second p-MOS transistor, forming a first connection node therebetween, the first connection node operatively connected to said output node of said first inverter circuit; and a third n-MOS transistor operatively connected to said delay circuit, said second n-MOS transistor and ground, and wherein said second inverter circuit comprises: a third p-MOS transistor, operatively connected to the power supply and the input terminal; a fourth p-MOS transistor operatively connected to said third p-MOS transistor and said delay circuit; and a fourth n-MOS transistor, operatively connected to ground, the input terminal, and operatively connected in series with said fourth p-MOS transistor, forming a second connection node therebetween, the second connection node operatively connected to the output node of said second inverter.

Claim 10

A buffer circuit as set forth in claim 7, further comprising: a first terminal operatively connected to receive and supply an output enable signal; and a second terminal operatively connected to receive and supply an inverted output enable signal; and wherein said first inverter circuit further comprises: a fifth p-MOS transistor, operatively connected in parallel with said second p-MOS transistor and operatively connected to said first terminal; a fifth n-MOS transistor, operatively connected to said first terminal, said third n-MOS transistor and ground; and wherein said second inverter circuit further comprises: a sixth p-MOS transistor operatively connected to said second terminal, the power supply and said third p-MOS transistor; and a sixth n-MOS transistor, operatively connected to said second terminal and in parallel with said fourth n-MOS transistor.

Claim 11

A buffer circuit as set forth in claim 6, further comprising: a first inverter operatively connected between the input terminal and said input node of said first inverter circuit; a second inverter operatively connected between said input node of said second inverter circuit and the input terminal; and a third inverter operatively connected between said delay circuit and said second inverter circuit; wherein said first inverter circuit comprises: a second n-MOS transistor operatively connected to the power supply and said input node of said first inverter circuit; a third n-MOS transistor operatively connected to the input terminal and connected in series with said second n-MOS transistor forming a first connection node therebetween, the first connection node operatively connected to the first p-MOS transistor; and a fourth n-MOS transistor, operatively connected to said delay circuit, said third n-MOS transistor and ground; and wherein said second inverter circuit comprises: a fifth n-MOS transistor, operatively connected to the power supply and said input node of said second inverter circuit; a sixth n-MOS transistor operatively connected to said third inverter and in series with said fifth n-MOS transistor; and a seventh n-MOS transistor, operatively connected to ground, the input terminal and connected in series with said sixth n-MOS transistor forming a second connection node therebetween, the second connection node operatively connected to the first n-MOS transistor.