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US5025181A Expired / Lapsed US ⏱️ 0.0 years remaining

Apparatus for generating digital gating signals in response to a digital data signal

Assignee: Advanced Micro Devices Inc
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Filing: 1990-08-31
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Granted: 1991-06-18
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Expires: 2010-08-31
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Abstract

Abstract An apparatus for generating digital gating signals respectively on an N-channel and a P-channel drive line in response to a digital data signal comprising a first and a second digital switching device, a resistive device, and first and second threshold devices for generating digital signals when receiving an input signal which exceeds a preestablished threshold value. The first and second digital switching devices commonly receive the data signal at their respective gates. The first digital switching device is operatively connected between a voltage source and the resistive device and generates a first gating signal from a juncture intermediate the first digital switching device and the resistive device. The second digital switching device is operatively connected between the resistive device and ground and generates a second gating signal from a juncture intermediate the resistive device and the second digital switching device. The first threshold device has a first preestablished threshold value, receives the first gating signal as its input signal, and generates a first digital signal representative of the first gating signal; the second threshold device has a second preestablished threshold value, receives the second gating signal as its input signal, and generates a second digital signal representative of the second gating signal. The first preestablished threshold value is preferably lower than the second preestablished threshold value.

Inventors

  • 👤 Charles Farmer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 19:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 252 words
An apparatus for generating a pair of digital gating signals in response to a digital data signal, the apparatus comprising: a first and a second digital switching means for switching digital signals; a resistive means for establishing resistance in a circuit path; and first and second threshold means for generating digital signals when receiving an input signal which exceeds a preestablished threshold value; said first and second digital switching means commonly receiving said data signal at their respective gates; said first digital switching means being operatively connected between a voltage source and said resistive means and generating a first gating signal of said pair of gating signals intermediate said first digital switching means and said resistive means; said second digital switching means being operatively connected between said resistive means and ground and generating a second gating signal of said pair of gating signals intermediate said resistive means and said second digital switching means; said first threshold means having a first preestablished threshold value receiving said first gating signal as said input signal, and generating a first digital signal representative of said first gating signal; said second threshold means having a second preestablished threshold value, receiving said second gating signal as said input signal, and generating a second digital signal representative of said second gating signal; said first digital switching means being configured as a pull-up digital switch, said second switching means being configured as a pull-down digital switch, and said first preestablished threshold value being lower than said second preestablished threshold value.
Claim 2
Independent Claim 252 words
An apparatus for generating a pair of digital gating signals in response to a digital data signal, the apparatus comprising: a first and a second digital switching means for switching digital signals; a resistive means for establishing resistance in a circuit path; and first and second threshold means for generating digital signals when receiving an input signal which exceeds a preestablished threshold value; said first and second digital switching means commonly receiving said data signal at their respective gates; said first digital switching means being operatively connected between a voltage source and said resistive means and generating a first gating signal of said pair of gating signals intermediate said first digital switching means and said resistive means; said second digital switching means being operatively connected between said resistive means and ground and generating a second gating signal of said pair of gating signals intermediate said resistive means and said second digital switching means; said first threshold means having a first preestablished threshold value receiving said first gating signal as said input signal, and generating a first digital signal representative of said first gating signal; said second threshold means having a second preestablished threshold value, receiving said second gating signal as said input signal, and generating a second digital signal representative of said second gating signal; said first digital switching means being configured as a pull-up digital switch, said second switching means being configured as a pull-down digital switch, and said first preestablished threshold value being lower than said second preestablished threshold value.
Claim 3
Dependent Claim 48 words
An apparatus for generating a pair of digital gating signals in response to a digital data signal as recited in claim 1 wherein said first digital switching means comprises a P-channel field effect transistor device, and said second digital switching means comprises an N-channel field effect transistor device.
Claim 4
Dependent Claim 41 words
An apparatus for generating a pair of digital gating signals in response to a digital data signal as recited in claim 1 wherein said each of first and second threshold means comprise a threshold shifted inverter in series with an inverter.
Claim 5
Dependent Claim 41 words
An apparatus for generating a pair of digital gating signals in response to a digital data signal as recited in claim 2 wherein said each of first and second threshold means comprise a threshold shifted inverter in series with an inverter.

References Cited (Backward Citations)

US4682954A Cited
US4074150A Cited
US4408135A Cited
US4567385A Cited
JPS6175618A Cited
US4916337A Cited
US4916337B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-06-17 1994-12-17 1995-06-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-06-17 1998-12-17 1999-06-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-06-17 2002-12-17 2003-06-18 $7700.00 Window Closed / Lapsed

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