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JPS6175618A Expired / Lapsed JP ⏱️ 0.0 years remaining

Complementary bimis tri-state gate circuit

Assignee: Fujitsu Ltd
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Filing: 1984-09-21
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Granted: —
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Expires: 2004-09-21
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Abstract

Abstract PURPOSE:To prevent much rash current from flowing by using a bipolar transistor (TR) for an output stage and using a CMOS circuit for a pre-stage so as to turn on the bipolar TR requiring a large drive current at transient state. CONSTITUTION:The range of input voltages where the bipolar TRs are at off/off state is adjusted by combining CMOS TRs, the bipolar TRs and resistors so as to avoid completely the on/on state of the bipolar TRs. When an enable signal Tc goes to a low level, since both a PCMO TRP3 and an NMOS TRN3 are turned on, the base potential of the PNP TRT1 goes to a high level and the base potential of the NPNT2 goes to a low level. Thus, since the PNPTRT1 and the NPNTRT2 are both turned off forcibly, the input signal VIN is changed to a high or a low level, and the output OT is kept to a high impedance state.

Inventors

  • 👤 Satoru Tanizawa
  • 👤 谷澤 哲

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 01:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5057161A Cited
JPS5060174A Cited
JPS5490941A Cited

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