US4916337A
Expired / Lapsed
US
⏱️ 0.0 years remaining
TTL to CMOS logic level translator
Assignee: Renesas Electronics America Inc
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Filing: 1989-03-07
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Granted: 1990-04-10
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Expires: 2009-03-07
Abstract
Abstract Four transistors, a pair of buffers, and an inverter are configured with the first transistor connected in a pull-up configuration, with the transistor drain connected to a first node and with the transistor gate connected to a second node. The second transistor is connected in a pull-down configuration, with the transistor gate connected to a (data) input line and with the transistor drain connected to the first node. The third transistor is also connected in the pull-up configuration, with the transistor gate connected to the first node and with the transistor drain connected to the second node. The fourth transistor is also connected in the pull-down configuration, with the transistor gate coupled by the inverter to the input line and with the transistor drain connected to the second node. The buffers are each connected between a respective one of the nodes and a respective one of two (data) output lines.
Inventors
- 👤 Wingyu Leung
- 👤 Winston K. M. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:52
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
167 words
A TTL to CMOS logic level translator comprising in combination: an input line; a pair of nodes including a first node and a second node; an output line coupled to a predetermined one of said pair of nodes; inverter means having an input connected to said input line and an output; a first transistor having source means connected to receive a first power supply potential, drain means connected to said first node, and a gate connected to said second node; a second transistor having a gate connected to said input line, drain means connected to said first node, and source means connected to receive a second power supply potential; a third transistor having source means connected to receive said first power supply potential, drain means connected to said second node, and a gate connected to said first node; a fourth transistor having a gate connected to said inverter output, drain means connected to said second node, and source means connected to receive said second power supply potential.
Claim 2
Dependent Claim
167 words
A TTL to CMOS logic level translator comprising in combination: an input line; a pair of nodes including a first node and a second node; an output line coupled to a predetermined one of said pair of nodes; inverter means having an input connected to said input line and an output; a first transistor having source means connected to receive a first power supply potential, drain means connected to said first node, and a gate connected to said second node; a second transistor having a gate connected to said input line, drain means connected to said first node, and source means connected to receive a second power supply potential; a third transistor having source means connected to receive said first power supply potential, drain means connected to said second node, and a gate connected to said first node; a fourth transistor having a gate connected to said inverter output, drain means connected to said second node, and source means connected to receive said second power supply potential.
Claim 3
Dependent Claim
180 words
A TTL to CMOS logic level translator comprising in combination: an input line; a pair of nodes including a first node and a second node; an output line; a buffer having an input connected to a predetermined one of said pair of nodes and an output connected to said output line; inverter means having an input connected to said input line and an output; a first transistor having source means connected to receive a first power supply potential, drain means connected to said first node, and a gate connected to said second node; a second transistor having a gate connected to said input line, drain means connected to said first node, and source means connected to receive a second power supply potential; a third transistor having source means connected to receive said first power supply potential, drain means connected to said second node, and a gate connected to said first node; a fourth transistor having a gate connected to said inverter output, drain means connected to said second node, and source means connected to receive said second power supply potential.
Claim 4
Dependent Claim
180 words
A TTL to CMOS logic level translator comprising in combination: an input line; a pair of nodes including a first node and a second node; an output line; a buffer having an input connected to a predetermined one of said pair of nodes and an output connected to said output line; inverter means having an input connected to said input line and an output; a first transistor having source means connected to receive a first power supply potential, drain means connected to said first node, and a gate connected to said second node; a second transistor having a gate connected to said input line, drain means connected to said first node, and source means connected to receive a second power supply potential; a third transistor having source means connected to receive said first power supply potential, drain means connected to said second node, and a gate connected to said first node; a fourth transistor having a gate connected to said inverter output, drain means connected to said second node, and source means connected to receive said second power supply potential.
Claim 5
Dependent Claim
148 words
A TTL to CMOS logic level translator comprising in combination: an input line; a first node; a second node; inverter means having an input connected to said input line and an output; a first transistor having source means connected to receive a first power supply potential, drain means connected to said first node, and a gate connected to said second node; a second transistor having a gate connected to said input line, drain means connected to said first node, and source means connected to receive a second power supply potential; a third transistor having source means connected to receive said first power supply potential, drain means connected to said second node, and a gate connected to said first node; a fourth transistor having a gate connected to said inverter output, drain means connected to said second node, and source means connected to receive said second power supply potential.
Claim 6
Dependent Claim
148 words
A TTL to CMOS logic level translator comprising in combination: an input line; a first node; a second node; inverter means having an input connected to said input line and an output; a first transistor having source means connected to receive a first power supply potential, drain means connected to said first node, and a gate connected to said second node; a second transistor having a gate connected to said input line, drain means connected to said first node, and source means connected to receive a second power supply potential; a third transistor having source means connected to receive said first power supply potential, drain means connected to said second node, and a gate connected to said first node; a fourth transistor having a gate connected to said inverter output, drain means connected to said second node, and source means connected to receive said second power supply potential.
Claim 7
Dependent Claim
31 words
A TTL to CMOS logic level translator as recited in claim 3 further comprising a first output line and first buffer means coupling said first node to said first output line.
Claim 8
Dependent Claim
31 words
A TTL to CMOS logic level translator as recited in claim 4 further comprising a second output line and second buffer means coupling said second node to said second output line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-09 | 1993-10-09 | 1994-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-09 | 1997-10-09 | 1998-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-09 | 2001-10-09 | 2002-04-10 | $7700.00 | Window Closed / Lapsed |