TTL-CMOS input buffer

Claim 1

An interface circuit on an integrated circuit chip, said chip having a CMOS logic circuit to be driven from an external TTL logic circuit, said chip having a pair of terminals connected to a supply voltage, said interface circuit comprising: CMOS intverter means having an input for receiving logic level signals from said TTL logic circuit and an output operatively connected to an input of said CMOS logic circuit, said inverter means having an input switching voltage level at which a binary logic level signal at said output changes level, said switching voltage dependent upon the value of said supply voltage, the temperature of said chip, and with the fabrication process of said chip, and in which said switching voltage level is controllable by a bias voltage; and bias voltage generation means on said chip having an output bias voltage connected to said inverter means, said bias voltage generation means connected between said pair of supply voltage terminals, said bias generation means having active voltage divider means connected to said inverter means for supplying a bias voltage less than a voltage across said supply voltage terminals in which said bias voltage varies with said supply voltage, with the temperature of said chip, and with variations in the process of fabrication of said logic chip whereby said switching voltage level of said inverter means is stabilized.

Claim 3

A device for conditioning TTL logic signals for operation of CMOS logic circuitry disposed on a semiconductor chip comprising: (a) an input on said chip for receiving said TTL signals; (b) a CMOS inverter/buffer on said chip connected between a pair of supply voltage terminals and having a signal input connected to receive said TTL signals, an output connected to said CMOS logic circuitry on said chip, and means connected to said CMOS inverter/buffer, said means having a bias voltage input, said inverter/buffer having a preselected voltage level at which the logic level at said output switches; and (c) a CMOS bias generator on said chip connected between said pair of supply voltage terminals, said bias generator having active voltage divider means connected to said inverter/buffer bias voltage input for producing a bias voltage less than a voltage across said voltage terminals in which said bias voltage is applied to said bias voltage input and varies with said supply voltage, with the temperature of said chip, and with variations in the process of fabrication of said logic chip whereby said switching voltage level of said inverter/buffer is stabilized, said bias generator including: (i) a first N-channel transistor and a first P-channel transistor connected as as first voltage divider across said supply voltage terminals to produce a precompensation bias voltage at an output thereof, (ii) a second P-channel transistor having its gate connected to said first voltage divider output, said second P-channel transistor connected to a pair of N-channel tranisistors, said second P-channel transistors serving as a second voltage divider across across said supply voltage terminals to produce said bias voltage at said bias voltage input, and (iii) a bias voltage line on said chip for supplying said bias voltage to a plurality of CMOS logic circuits disposed on said chip.

Claim 4

A device for conditioning TTL logic signals for operation of CMOS logic circuitry disposed on a semiconductor chip comprising: (a) an input on said chip for receiving said TTL signals; (b) a CMOS inverter/buffer on said chip connected between a pair of supply voltage terminals and having a signal input connected to receive said TTL signals, an output connected to said CMOS logic circuitry on said chip, and means connected to said CMOS inverter/buffer, said means having a bias voltage input, said inverter/buffer having a preselected voltage level at which the logic level at said output switches; and (c) a CMOS bias generator on said chip connected between said pair of supply voltage terminals, said bias generator having active voltage divider means connected to said inverter/buffer bias voltage input for producing a bias voltage less than a voltage across said voltage terminals in which said bias voltage is applied to said bias voltage input and varies with said supply voltage, with the temperature of said chip, and with variations in the process of fabrication of said logic chip whereby said switching voltage level of said inverter/buffer is stabilized, said bias generator including: (i) a first N-channel transistor and a first P-channel transistor connected as as first voltage divider across said supply voltage terminals to produce a precompensation bias voltage at an output thereof, (ii) a second P-channel transistor having its gate connected to said first voltage divider output, said second P-channel transistor connected to a pair of N-channel tranisistors, said second P-channel transistors serving as a second voltage divider across across said supply voltage terminals to produce said bias voltage at said bias voltage input, and (iii) a bias voltage line on said chip for supplying said bias voltage to a plurality of CMOS logic circuits disposed on said chip.

Claim 8

A device for conditioning TTL logic level signals for operation of CMOS logic circuitry disposed on a semiconductor chip comprising: an input on said chip for receiving said TTL signals; a CMOS inverter/buffer on said chip connected between a pair of supply voltage terminals and having a signal input connected to receive said TTL signals, an output connected to receive said TTL signals, an output connected to said CMOS logic circuitry on said chip, and means connected to said CMOS inverter/buffer, said means having a bias voltage input, said inverter/buffer having a preselected voltage level at which the logic level at said output switches; and a CMOS bias generator on said chip connected between said pair of supply voltage terminals, said bias generator having active voltage divider means connected to said inverter/buffer bias voltage input for producing a bias voltage less than a voltage across said supply voltage terminals in which said bias voltage is applied to said bias voltage input and varies with said supply voltage, with the temperature of said chip, and with variations in the process of fabrication of said logic chip whereby said switching voltage level of said inverter/buffer is stabilized.

Claim 9

A device for conditioning TTL logic level signals for operation of CMOS logic circuitry disposed on a semiconductor chip comprising: an input on said chip for receiving said TTL signals; a CMOS inverter/buffer on said chip connected between a pair of supply voltage terminals and having a signal input connected to receive said TTL signals, an output connected to receive said TTL signals, an output connected to said CMOS logic circuitry on said chip, and means connected to said CMOS inverter/buffer, said means having a bias voltage input, said inverter/buffer having a preselected voltage level at which the logic level at said output switches; and a CMOS bias generator on said chip connected between said pair of supply voltage terminals, said bias generator having active voltage divider means connected to said inverter/buffer bias voltage input for producing a bias voltage less than a voltage across said supply voltage terminals in which said bias voltage is applied to said bias voltage input and varies with said supply voltage, with the temperature of said chip, and with variations in the process of fabrication of said logic chip whereby said switching voltage level of said inverter/buffer is stabilized.