Voltage level translating circuit

Claim 2

A voltage level translating circuit providing between its output terminals a first output signal having a voltage level within a first predetermined range in response to a first input signal at its input terminal having a voltage level within a second predetermined range, and a second output signal having a voltage level within a third predetermined range in response to a second input signal having a voltage level within a fourth predetermined range, the voltage level translating circuit including in combination: first switch means having first, second and control electrodes, said control electrode being connected directly to the input terminal; first circuit means for applying a first supply voltage connected to said second electrode of said first switch means; first load means having a first terminal connected to said first electrode of said first switch means and a second terminal; second circuit means for applying a second supply voltage connected to said second terminal of said first load means; second load means having a first terminal connected to one of the output terminals and a second terminal connected to said second circuit means; second switch means having a first electrode connected directly to one of the output terminals and to said first terminal of said second load means, a control electrode connected to said control electrode of said first switch means, and a second electrode connected to said first electrode of said first switch means; said first switch means respectively providing first and second control voltages at its first electrode in response to the first and second input signals; and said second switch means being rendered respectively conductive and nonconductive in response to said first and said second control voltages at said second electrode thereof and said first and second input signals at said control electrode thereof, to respectively provide the first and second output signals between the output terminals.

Claim 3

The voltage level translating circuit of claim 1 wherein said first and second switch means respectively include first and second low threshold, metal oxide semiconductor transistor devices each having source, gate, drain and substrate electrodes.

Claim 4

The voltage level translating circuit of claim 2 wherein said substrate terminal of said second transistor is connected to said first circuit means, said substrate and said source of said second transistor having conductivity types such that said second control voltage at said first electrode of said first transistor and said first supply voltage tend to reverse bias the source-to-substrate junction of said second transistor as it is rendered nonconductive so that the threshold voltage of said second transistor increases to hold said second transistor in a nonconductive state in response to the existence of the second input signal.

Claim 5

The voltage level translating circuit of claim 2 wherein said first and second transistors are of the P-channel, enhancement-mode type.

Claim 6

The voltage level translating circuit of claim 1 wherein said first and second load means respectively include third and fourth low threshold, metal oxide semiconductor transistors having source, gate and drain electrodes, said source electrodes forming said first terminals of said first and second load means, said gate and drain electrodes of each of said third and fourth transistors being connected together to form said second terminals of each of said load means.

Claim 7

A logic level translating circuit which responds to a logical ''''one'''' input signal to provide a first output level and to a logical ''''zero'''' input signal to provide a second output level, including in combination: first and second low threshold, metal oxide semiconductor field effect transistors each having source, gate and drain electrodes, said drain electrode of the first transistor being connected to said source electrode of said second transistor, means connecting said source electrode of said first transistor and said drain electrode of said second transistor respectively to first and second voltage supplies, said gate electrode of said first transistor being directly connected to an input terminal and said gate electrode of said second transistor being connected to its drain to form a first load, said first transistor having a first conductance in response to the logical ''''zero'''' input signal to provide a first control signal at its drain electrode and a second conductance which is less than said first conductance in response to the logical ''''one'''' input signal to provide a second control signal at its drain electrode; a third low threshold metal oxide semiconductor, field effect transistor having a gate electrode directly connected to both the input terminal and to said gate electrode of said first transistor, a source electrode connected to said drain electrode of said first transistor, and a drain electrode connected directly to an output terminal; a fourth low threshold metal oxide semiconductor transistor having gate and drain electrodes connected to said second supply to form a second load and a source electrode connected directly to said drain electrode of said third transistor; and said third transistor being rendered conductive in response to said first control signal so that the first output level is applied from said first voltage supply through said third transistor to the output terminal, and said third transistor being rendered substantially nonconductive in response to said second control signal so that the second output level is applied from said voltage supply through said fourth transistor to the output terminal.

Claim 8

A logic level translating circuit which responds to a logical ''''one'''' input signal to provide a first output level and to a logical ''''zero'''' input signal to provide a second output level, including in combination: first and second low threshold, metal oxide semiconductor field effect transistors each having source, gate and drain electrodes, said drain electrode of the first transistor being connected to said source electrode of said second transistor, means connecting said source electrode of said first transistor and said drain electrode of said second transistor respectively to first and second voltage supplies, said gate electrode of said first transistor being directly connected to an input terminal and said gate electrode of said second transistor being connected to its drain to form a first load, said first transistor having a first conductance in response to the logical ''''zero'''' input signal to provide a first control signal at its drain electrode and a second conductance which is less than said first conductance in response to the logical ''''one'''' input signal to provide a second control signal at its drain electrode; a third low threshold metal oxide semiconductor, field effect transistor having a gate electrode directly connected to both the input terminal and to said gate electrode of said first transistor, a source electrode connected to said drain electrode of said first transistor, and a drain electrode connected directly to an output terminal; a fourth low threshold metal oxide semiconductor transistor having gate and drain electrodes connected to said second supply to form a second load and a source electrode connected directly to said drain electrode of said third transistor; and said third transistor being rendered conductive in response to said first control signal so that the first output level is applied from said first voltage supply through said third transistor to the output terminal, and said third transistor being rendered substantially nonconductive in response to said second control signal so that the second output level is applied from said voltage supply through said fourth transistor to the output terminal.

Claim 9

The logic translating circuit of claim 6 wherein said first load formed by said second transistor has substantially more resistance than said second load formed by said fourth transistor thereby enabling said first transistor to have a small geometry as compared to the geometry of said third transistor.

Claim 10

The logic level translating circuit of claim 6 wherein said third transistor includes a substrate terminal which is connected to said first voltage supply, said second control signal in cooperation with said first power supply voltage tending to reverse bias the source-to-substrate junction of said third transistor and thereby raise its threshold voltage in response to the logical ''''one'''' being applied to the input terminal.