US3590273A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four phase logic systems
Assignee: US Philips Corp
•
Filing: 1969-02-14
•
Granted: 1971-06-29
•
Expires: 1989-02-14
Abstract
Abstract An interface circuit for connecting two chips of a four phase MOST integrated circuit uses four interconnected MOST''s switched by the alternate and nonconcurrent pulses of two separate phases of a group of four phase clock signals.
Inventors
- 👤 Denis Brian Jarvis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
226 words
An interface for interconnecting two chips of an integrated four-phase logic system, comprising a first MOST on a first of the two chips and having source, drain and gate terminals, the gate terminal of the first MOST comprising the input terminal of the interface, means for connecting the source terminal of the first MOST to ground, a second MOST on the second of the two chips having source, drain and gate terminals, a third MOST on the second chip having source, drain and gate terminals, a fourth MOST on the second chip having source, drain and gate terminals, means for connecting the drain terminal of the first MOST to the gate terminal of the third MOST and to the source terminal of the second MOST, means for interconnecting the drain terminal of the third MOST with the source terminal of the fourth MOST, the source terminal of the fourth MOST comprising the output terminal of the interface, means for connecting the gate and drain terminals of the second MOST to an input terminal for a first phase of spaced clock pulses, and means for connecting the gate and drain terminals of the fourth MOST and the source terminal of the third MOST to an input terminal for a third phase of spaced clock pulses occurring alternately and nonconcurrently with the clock pulses of the first phase.
Claim 2
Dependent Claim
226 words
An interface for interconnecting two chips of an integrated four-phase logic system, comprising a first MOST on a first of the two chips and having source, drain and gate terminals, the gate terminal of the first MOST comprising the input terminal of the interface, means for connecting the source terminal of the first MOST to ground, a second MOST on the second of the two chips having source, drain and gate terminals, a third MOST on the second chip having source, drain and gate terminals, a fourth MOST on the second chip having source, drain and gate terminals, means for connecting the drain terminal of the first MOST to the gate terminal of the third MOST and to the source terminal of the second MOST, means for interconnecting the drain terminal of the third MOST with the source terminal of the fourth MOST, the source terminal of the fourth MOST comprising the output terminal of the interface, means for connecting the gate and drain terminals of the second MOST to an input terminal for a first phase of spaced clock pulses, and means for connecting the gate and drain terminals of the fourth MOST and the source terminal of the third MOST to an input terminal for a third phase of spaced clock pulses occurring alternately and nonconcurrently with the clock pulses of the first phase.
Claim 3
Dependent Claim
16 words
An interface as claimed in claim 1, wherein each of the MOSTS are P-channel enhancement MOSTS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-28 | 1974-12-28 | 1975-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-28 | 1978-12-28 | 1979-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-28 | 1982-12-28 | 1983-06-29 | $7700.00 | Window Closed / Lapsed |