US3591857A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Most translating and gating circuit
Assignee: US Philips Corp
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Filing: 1969-02-14
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Granted: 1971-07-06
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Expires: 1989-02-14
Abstract
Abstract A circuit for a four phase logic system wherein the necessity for a separate bias voltage is eliminated by connecting the source-drain path of an input MOST to the source-drain path of a higher impedance second MOST and by connecting both the gate and drain terminals of the second MOST to a source of clock pulses.
Inventors
- 👤 Denis Brian Jarvis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:57
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
216 words
A circuit for a four-phase logic system comprising a first MOST having gate, source and drain terminals, the gate terminal of the first MOST comprising the input terminal of the circuit, means for connecting the source terminal of the first MOST to ground, a second MOST having source, drain and gate terminals, the resistance between the drain and source terminals of the second MOST having a larger value than the resistance between the source and drain terminals of the first MOST for a given voltage on the gate terminals of each of the first and second MOST''s, means for connecting the drain terminal of the first MOST to the source terminal of the second MOST, a third MOST having source, drain and gate terminals, means for connecting the source terminals of the second and third MOST''s, means for connecting the gate terminal and drain terminal of the second MOST and the gate of the third MOST to a source of clock pulses, a fourth MOST having source, drain and gate terminals, the drain terminal of the fourth MOST comprising the output terminal of the circuit, means for connecting the source terminal of the fourth MOST to ground, and means for connecting the gate terminal of the fourth MOST to the drain terminal of the third MOST.
Claim 2
Dependent Claim
216 words
A circuit for a four-phase logic system comprising a first MOST having gate, source and drain terminals, the gate terminal of the first MOST comprising the input terminal of the circuit, means for connecting the source terminal of the first MOST to ground, a second MOST having source, drain and gate terminals, the resistance between the drain and source terminals of the second MOST having a larger value than the resistance between the source and drain terminals of the first MOST for a given voltage on the gate terminals of each of the first and second MOST''s, means for connecting the drain terminal of the first MOST to the source terminal of the second MOST, a third MOST having source, drain and gate terminals, means for connecting the source terminals of the second and third MOST''s, means for connecting the gate terminal and drain terminal of the second MOST and the gate of the third MOST to a source of clock pulses, a fourth MOST having source, drain and gate terminals, the drain terminal of the fourth MOST comprising the output terminal of the circuit, means for connecting the source terminal of the fourth MOST to ground, and means for connecting the gate terminal of the fourth MOST to the drain terminal of the third MOST.
Claim 3
Dependent Claim
18 words
A circuit as claimed in claim 1, wherein each of the MOST''s are of the P-channel enhancement type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-05 | 1975-01-04 | 1975-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-05 | 1979-01-04 | 1979-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-05 | 1983-01-04 | 1983-07-06 | $7700.00 | Window Closed / Lapsed |