Interface circuit for coupling bipolar to field effect transistors

Claim 1

In combination with a field effect transistor logic array which requires a first level of threshold voltage for driving into conduction the field effect transistor array and, a bipolar transistor driver circuit as a source of first level and second level driving signals which of themselves have a magnitude insufficient to act directly as drive voltage signals for the array, a coupling circuit responsive to said bipolar transistor driver for amplifying the drive voltage supplied by the bipolar transistor logic driver and for applying the amplified drive signals to said field effect transistor logic array, comprising: a plurality of field effect transistors and each having source, drain, gate and substrate terminals and said plurality of field effect transistors being connected in series arrangement whereby the source of the first is connected to the drain of the next; a first potential source having a first potential level, a second potential level and a third potential level, and said first potential level being more negative than said second potential level and said third potential level being more negative than said first potential level; said drain terminal of the first field effect transistor in the series being connected to said first potential level and the source terminal of the last transistor in the series being connected to said second potential level; certain of said serially connected transistors providing a predetermined voltage drop over each thereof for controlling the operation of the remaining transistors in said series, and the gates of these voltage dropping transistors being connected together and being further connected to said third potential level for biasing said voltage dropping transistor into conduction and for establishing a bias potential at a first junction formed at the connection of the source and drain terminals of said voltage dropping transistor; the gate terminal of a remaining serially connected transistor being connected to the drain terminal of the same transistor for developing a voltage which is proportional to the threshold voltage of the field effect transistor logic array; an amplifying field effect transistor having source, drain, gate and substrate terminals, and having its gate terminal connected to said first junction and being responsive to said bias potential, and having its source terminal responsive to the first level drive signal from the bipolar circuit and the second level drive signal from the bipolar circuit; a field effect transistor having source, drain, gate and substrate terminals and having its drain terminal connected to said first potential level and having its gate terminal connected to said third potential level and having its source terminal connected to said drain terminal of said amplifying transistor at a second junction as the source of amplified driving signals for the field effect transistor logic array; said amplifying transistor responding to said bias potential on its gate electrode and said first level of driving signals from said bipolar driver to conduct for lowering the voltage at said second junction and generating a disabling logic driving signal, and said amplifying transistor responding to said bias potential on its gate electrode and said second level of driving signals from said bipolar driver to stop conducting for raising the voltage at said second junction and generating a disabling logic driving signal; and said substrate terminals of each of said previously identified field effect transistors being connected to said second voltage level.