US4048518A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS buffer circuit
Assignee: Intel Corp
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Filing: 1976-12-27
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Granted: 1977-09-13
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Expires: 1996-12-27
Abstract
Abstract An MOS buffer circuit particularly suitable as an input stage for receiving a lower level input signal in an MOS integrated circuit. A transistor is employed to decouple an input transistor from a load, thereby allowing an output signal from the circuit to rise more quickly.
Inventors
- 👤 James T. Koo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 00:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
111 words
In an MOS inverter which includes an input transistor coupled in series with a load means, an improvement comprising: a decoupling transistor coupled between said load means and said input transistor; the gate of said decoupling transistor being coupled to a controlled variable potential means for controlling the gate potential of said decoupling transistor in response to a change of voltage on the gate of said input transistor; whereby the voltage changes on the respective gates of said input transistor and said decoupling transistor together cause said decoupling transistor to rapidly decouple said input transistor from said load means, thereby allowing the output signal from said inverter to charge more quickly.
Claim 2
Dependent Claim
111 words
In an MOS inverter which includes an input transistor coupled in series with a load means, an improvement comprising: a decoupling transistor coupled between said load means and said input transistor; the gate of said decoupling transistor being coupled to a controlled variable potential means for controlling the gate potential of said decoupling transistor in response to a change of voltage on the gate of said input transistor; whereby the voltage changes on the respective gates of said input transistor and said decoupling transistor together cause said decoupling transistor to rapidly decouple said input transistor from said load means, thereby allowing the output signal from said inverter to charge more quickly.
Claim 3
Dependent Claim
122 words
An MOS circuit for providing an output signal in response to an input signal comprising: load means coupled to a source of potential; a decoupling transistor coupled to said load means; an input transistor coupled to said decoupling transistor, the gate of said input transistor being coupled to receive said input signal; and, control means for controlling the potential on the gate of said decoupling transistor comprising, a first transistor having its gate coupled to the common terminal between said input transistor and said decoupling transistor, and one of its terminals coupled to said gate of said decoupling transistor; whereby said decoupling transistor decoupled capacitance associated with said input transistor thereby permitting said output signal of said circuit to rise more quickly.
Claim 4
Dependent Claim
122 words
An MOS circuit for providing an output signal in response to an input signal comprising: load means coupled to a source of potential; a decoupling transistor coupled to said load means; an input transistor coupled to said decoupling transistor, the gate of said input transistor being coupled to receive said input signal; and, control means for controlling the potential on the gate of said decoupling transistor comprising, a first transistor having its gate coupled to the common terminal between said input transistor and said decoupling transistor, and one of its terminals coupled to said gate of said decoupling transistor; whereby said decoupling transistor decoupled capacitance associated with said input transistor thereby permitting said output signal of said circuit to rise more quickly.
Claim 5
Dependent Claim
22 words
The MOS circuit defined by claim 2 wherein said control means includes charging means for charging said gate of said decoupling transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-12 | 1981-03-14 | 1981-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-12 | 1985-03-14 | 1985-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-12 | 1989-03-14 | 1989-09-13 | $7700.00 | Window Closed / Lapsed |