Mos circuit with nodal capacitor predischarging means

Claim 2

In a multiphase clocked type inverter circuit of the type including a plurality of metal-oxide-semiconductor elements, definable as MOS elements, each element being switchable to an ON state when the potential at a gate terminal thereof is a first value, the element being in an OFF state when the gate potential is of a second value, said circuit including internal nodal capacitors and an output capacitor which are prechargable to said first value from a first reference potential at said first value during a first clocking phase and which are conditionally dischargable to a second reference potential of said second value during a subsequent second clocking phase, said circuit further including control MOS element means which include at least one control MOS element which is switchable to the ON state for at least a limited duration during a third clocking phase, preceding said first phase, the arrangement comprising: at least one predischarging control MOS element switchable to the ON state not after said third clocking phase for providing a discharge path to said internal nodal capacitors to a reference potential of said second value, whereby said internal nodal capacitors are discharged to said second value before said first clocking phase.

Claim 3

The arrangement as recited in claim 1 wherein said circuit includes a first internal nodal capacitor which is connected to said first reference potential through a first MOS element which is switchable to said ON state during said first phase, a second internal nodal capacitor connected to said second reference potential through a second MOS element which is switchable to said ON state during said second phase, third and fourth MOS elements connected in parallel between said first nodal capacitor and said output capacitor, said third and fourth MOS elements being switchable to their respective ON states during said first and second phase respectively, with said control MOS element means being connected between said fIrst and second internal nodal capacitors, and said at least one predischarging control MOS element being connected in series between said second reference potential and one of said internal nodal capacitors for providing a predischarge path for the nodal capacitor when said predischarging control MOS element is switchable to the ON state.

Claim 4

The arrangement as recited in claim 2 wherein said control MOS element means comprises a single control MOS element, connected between said first and second internal nodal capacitors and is switchable to said ON state during said third phase and said predischarging control MOS element is connected in series with said single control MOS element between said second reference potential and said first nodal capacitor and is switchable to said ON state during said third phase, whereby said first nodal capacitor is discharged to said second reference potential through said single control MOS element and said predischarging control MOS element and said second nodal capacitor is discharged to said second reference potential through said predischarging control MOS element during said third phase.

Claim 5

The arrangement as recited in claim 2 wherein said control MOS element means comprises a plurality of control MOS elements connected in parallel between said first and second internal nodal capacitors at least one of said control MOS elements being switchable to said ON state during said third phase and said predischarging control MOS element is connected in series with said control MOS elements between said second reference potential and said first nodal capacitor and is switchable to said ON state during said third phase, whereby said first nodal capacitor is discharged to said second reference potential through said at least one control MOS element and said predischarging control MOS element and said second nodal captor is discharged to said second reference potential through said predischarging control MOS element during said third phase.

Claim 6

The arrangement as recited in claim 2 wherein said control MOS element means include at least one group of control MOS elements connected in series between said first and second nodal capacitors and defining at least a third internal nodal capacitor, said control MOS elements being switchable to their respective ON state prior to said first phase, the circuit including a plurality of predischarging control MOS elements switchable to their ON states prior to said first phase for providing direct predischarge paths to said second reference potential for some of said nodal capacitors and for providing together with some of said control MOS elements which are ON predischarge paths for some others of said nodal capacitors; whereby prior to said first phase all of said nodal capacitors are substantially discharged to said second value.

Claim 7

The arrangement as recited in claim 2 wherein said control MOS element means include a plurality of control MOS elements connected in a preselected series-parallel combination between said first and second nodal capacitors and defining additional nodal capacitors therebetween, each MOS control element being switchable to an ON state prior to said first phase, the circuit including a plurality of predischarging control MOS elements switchable to their ON states prior to said first phase for providing direct predischarge paths to said second reference potential for some of said nodal capacitors and for providing, together with some of said control MOS elements which ON, predischarge paths for some others of said nodal capacitors, whereby prior to said first phase substantially all of said nodal capacitors are substantially discharged to said second value.

Claim 8

In an inverter type circuit of the type including a plurality of metal-oxide semiconductor elements, definable as MOS elements, including a precharging control MOS element switchable to an ON state during a first phase Period to enable the precharging of at least some of internal nodal capacitors of said circuit, a conditional discharging control MOS element switchable to an ON state during a second phase, subsequent said first phase, at least one input data control MOS element, connected between said precharging control MOS element and said conditional discharging control MOS element, and being switchable to an ON state during a third phase preceding said first phase and conditionally remaining in said ON state or conditionally switchable to an OFF state as a function of binary data supplied thereto prior to said second phase, whereby during said second phase all of said internal nodal capacitors are discharged only if said at least one input data control MOS element is in the ON state, the improvement comprising: at least one predischarging control MOS element switchable to an ON state not after said third phase for providing together with said input data control MOS element a discharge path for at least some of said internal nodal capacitors, whereby said internal nodal capacitors are discharged prior to said first phase.

Claim 9

In an inverter type circuit of the type including a plurality of metal-oxide semiconductor elements, definable as MOS elements, including a precharging control MOS element switchable to an ON state during a first phase Period to enable the precharging of at least some of internal nodal capacitors of said circuit, a conditional discharging control MOS element switchable to an ON state during a second phase, subsequent said first phase, at least one input data control MOS element, connected between said precharging control MOS element and said conditional discharging control MOS element, and being switchable to an ON state during a third phase preceding said first phase and conditionally remaining in said ON state or conditionally switchable to an OFF state as a function of binary data supplied thereto prior to said second phase, whereby during said second phase all of said internal nodal capacitors are discharged only if said at least one input data control MOS element is in the ON state, the improvement comprising: at least one predischarging control MOS element switchable to an ON state not after said third phase for providing together with said input data control MOS element a discharge path for at least some of said internal nodal capacitors, whereby said internal nodal capacitors are discharged prior to said first phase.

Claim 10

The arrangement as recited in claim 7 wherein said one predischarging control MOS element is switchable to said ON state during said third phase.

Claim 11

The arrangement as recited in claim 7 wherein said input data control MOS element is conditionally switchable to said OFF state as a function of the data supplied thereto during a phase after said third phase and not subsequent said first phase.

Claim 12

The arrangement as recited in claim 9 wherein said one predischarging control MOS element is switchable to said ON state during said third phase.

Claim 13

The arrangement as recited in claim 7 wherein said input data control MOS element is conditionally switchable to said OFF state or remains in said ON state as a function of the data supplied thereto during a fourth phase subsequent said third phase and preceding said first phase.

Claim 14

The arrangement as recited in claim 11 wherein said one predischarging control MOS element is switchable to said ON state during said third phase.

Claim 15

The arrangement as recited in claim 12 further including means coupled to said input data control MOS element and switchable to said ON state during said first phase for maintaining said input data control MOS element in an OFF state only if during said fourth phase said input data control MOS element was switched to said OFF state.

Claim 16

An inverter type circuit for providing a binary output which is either a first value or a second value as a function of the binary values of n inputs, comprising: a plurality of metal-oxide-semiconductor elements definable as MOS elements, each element being switchable to an ON state when the potential at a gate thereof is of said first value and is switchable to an OFF state when the gate thereof is of said second value; a first source of reference potential; a second source of reference potential; first means for connecting a first of said elements between said first source and a first node; second means for connecting a second of said elements between said second source and a second node; n third elements connected between said first and second nodes n being an integer equal to at least 1; a first nodal capacitor connected between said first node and said second source, said first element being switchable to said ON state during a first phase for precharging at least said first capacitor to said first source potential, and said second element being switchable to said ON state during a second phase following said first phase for providing at least said second capacitor with a discharge path to said second source, whereby said first capacitor is dischargeable to said second source when all serially connected third elements of at least one group of said third elements are in their ON state as a function of first value binary inpUts applied thereto through said third elements which are in their ON state; and at least a fourth MOS element switchable to said ON phase prior to said first phase and connected to at least one of said nodes and to said second source for predischarging at least said capacitor connected to said one node prior to said first phase.

Claim 17

An inverter type circuit for providing a binary output which is either a first value or a second value as a function of the binary values of n inputs, comprising: a plurality of metal-oxide-semiconductor elements definable as MOS elements, each element being switchable to an ON state when the potential at a gate thereof is of said first value and is switchable to an OFF state when the gate thereof is of said second value; a first source of reference potential; a second source of reference potential; first means for connecting a first of said elements between said first source and a first node; second means for connecting a second of said elements between said second source and a second node; n third elements connected between said first and second nodes n being an integer equal to at least 1; a first nodal capacitor connected between said first node and said second source, said first element being switchable to said ON state during a first phase for precharging at least said first capacitor to said first source potential, and said second element being switchable to said ON state during a second phase following said first phase for providing at least said second capacitor with a discharge path to said second source, whereby said first capacitor is dischargeable to said second source when all serially connected third elements of at least one group of said third elements are in their ON state as a function of first value binary inpUts applied thereto through said third elements which are in their ON state; and at least a fourth MOS element switchable to said ON phase prior to said first phase and connected to at least one of said nodes and to said second source for predischarging at least said capacitor connected to said one node prior to said first phase.

Claim 18

The arrangement as recited in claim 14 wherein n 1, the single third element being switchable to an ON state during a third phase preceding said first phase and being switchable to an OFF state or remaining in said ON state during a phase subsequent said third phase as a function of the binary level applied thereto during the phase subsequent said third phase, with said circuit including a single fourth element.

Claim 19

The arrangement as recited in claim 15 wherein said fourth element is switchable during said third phase, whereby said second capacitor is predischargeable during said third phase through said fourth element and said first capacitor is predischargable during said third phase through said third and fourth elements.

Claim 20

The arrangement as recited in claim 16 wherein binary data is applied to said third element to control its state during a fourth phase subsequent said third phase and prior to said first phase.