Logical bootstrapping in shift registers

Claim 2

In combination with a circuit integrated on a semiconductor substrate, means for selectively capacitively coupling a signal to a signal node comprising a field effect transistor having a gate terminal and an output circuit defined by spaced source and drain regions, a conductive channel being formed between said source and drain regions in response to a given potential difference between said gate terminal and one of said source and drain regions, said gate terminal being operatIvely connected to said signal node, and a pulse signal source operatively connected to at least one of said source and drain regions, and means for charging said signal node to a level corresponding to said given potential difference thereby to form said conductive channel in said substrate and to capacitively couple said pulse signal to said signal node.

Claim 3

The integrated circuit of claim 1, further comprising a second signal source and means responsive to said second signal source for selectively connecting said at least one of said source and drain regions to said first signal source.

Claim 4

The integrated circuit of claim 2, wherein said signal node is operatively connected to said second signal source independently of said field effect transistor, said second signal source comprising said charging means.

Claim 5

The integrated circuit of claim 2, wherein said first signal source is a clock signal source and said second signal source is a data signal source, said signal node being adapted to store a data signal.

Claim 6

The integrated circuit of claim 2, wherein said connecting means comprises a switching device having a control terminal operatively connected to said second signal source and an output circuit operatively connected between said first signal source and said at least one of said source and drain regions.

Claim 7

The integrated circuit of claim 5, wherein said signal node is operatively connected to said second signal source independently of said field effect transistor, said second signal source comprising said charging means.

Claim 8

The integrated circuit of claim 6, wherein said first signal source is a clock signal source and said second signal source is a data signal source, said signal mode being adapted to store a data signal.

Claim 9

The integrated circuit of claim 3, wherein said first signal source is a clock signal source and said second signal source is a data signal source, said signal node being adapted to store a data signal.

Claim 10

The circuit of claim 1, in which said pulse signal source is connected to both of said source and drain regions.

Claim 11

In a circuit adapted to shift data signals at one of two logic levels comprising a plurality of stages each having an input node and an output node, means to charge said output node to a first or second logic level corresponding to the signal at said input node, the improvement comprising a pulse signal source and means responsive to the logic level at said output node for selectively coupling said pulse signal source to said output node.

Claim 12

In a circuit adapted to shift data signals at one of two logic levels comprising a plurality of stages each having an input node and an output node, means to charge said output node to a first or second logic level corresponding to the signal at said input node, the improvement comprising a pulse signal source and means responsive to the logic level at said output node for selectively coupling said pulse signal source to said output node.

Claim 13

The circuit of claim 10, in which said coupling means is a capacitive coupling means.

Claim 14

The circuit of claim 10, wherein said coupling means comprises a switching device having a control terminal and first and second output terminals, said control terminal being connected to said output node and said first output terminal being connected to said signal source, and a coupling capacitor operatively connected between said second output terminal and said output node.

Claim 15

The circuit of claim 12, wherein said coupling capacitor comprises a field effect transistor having a gate terminal and an output circuit defined by a pair of source and drain regions, said gate terminal being connected to said output node and at least one of said source and drain regions being connected to said second output terminal of said switching device.

Claim 16

The circuit of claim 13, in which said second output terminal of said switching device is connected to both said source and drain regions.

Claim 17

A four-phase shift register comprising a plurality of stages connected in cascade, each having an input node and an output node, means for unconditionally charging the output node of one stage during a first clock interval, means responsive to the signal level at the input node of said one stage for conditionally discharging the output node thereof to a second logic level during a second interval, means for unconditionally charging the output node of the next stage during a third interval and Means, responsive to the signal level at the input node of said next stage, for conditionally discharging the output node thereof during a fourth interval, and so on for the remaining stages of said circuit, the improvement comprising a signal source and means operatively connected between said output node of said one stage and said signal source responsive to the level at said output node of said one stage, and effective to couple said signal source to said output node of said one stage during said fourth interval upon the occurrence of one only of said two logic levels at said output of said one stage.

Claim 18

A four-phase shift register comprising a plurality of stages connected in cascade, each having an input node and an output node, means for unconditionally charging the output node of one stage during a first clock interval, means responsive to the signal level at the input node of said one stage for conditionally discharging the output node thereof to a second logic level during a second interval, means for unconditionally charging the output node of the next stage during a third interval and Means, responsive to the signal level at the input node of said next stage, for conditionally discharging the output node thereof during a fourth interval, and so on for the remaining stages of said circuit, the improvement comprising a signal source and means operatively connected between said output node of said one stage and said signal source responsive to the level at said output node of said one stage, and effective to couple said signal source to said output node of said one stage during said fourth interval upon the occurrence of one only of said two logic levels at said output of said one stage.

Claim 19

The shift register of claim 15, in which said coupling means is a capacitive coupling means.

Claim 20

The shift register of claim 15, wherein said coupling means comprises a switching device having a control terminal and first and second output terminals, said control terminal being connected to said output node and said first output terminal being connected to said signal source, and a coupling capacitor operatively connected between said second output terminal and said output node.

Claim 21

The shift register of claim 17, wherein said coupling capacitor comprises a field effect transistor having a gate terminal and an output circuit defined by a pair of source and drain regions, said gate terminal being connected to said output node and at least one of said source and drain regions being connected to said second output terminal of said switching device.

Claim 22

The shift register of claim 18, wherein said second output terminal of said switching device is connected to both said source and drain regions.