US3601627A
Expired / Lapsed
US
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Multiple phase logic gates for shift register stages
Assignee: Boeing North American Inc
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Filing: 1970-07-13
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Granted: 1971-08-24
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Expires: 1990-07-13
Abstract
Abstract Logic gates having an isolation transistor connected to a common point between a load transistor and a two terminal logical network are combined at least partially with logic gates having the output connected to a common point between the load and isolation transistors for forming shift register stages.
Inventors
- 👤 Robert K Booher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
363 words
A multiple phase logic gate for shift register stages comprising a first stage having an output, a two terminal logical network comprising at least one field effect transistor haVing a control electrode, the signal on said control electrode determining the impedance of an electrical path from one terminal to the other, field effect transistor means and isolation field effect transistor means operable to conduct electrical current therethrough to one terminal of said logical network and to said output for simultaneously applying a voltage level to said one terminal of said logical network and to said output during a first phase recurring clock signal, said field effect transistor means operable to conduct electrical current therethrough only during said first phase recurring clock signal, means for applying a different voltage level to the other terminal of said logical network at least during a second phase recurring clock signal, said isolation field effect transistor means operable to conduct electrical current therethrough during said second phase recurring clock signal for connecting said one terminal to said output during said second phase recurring clock signal, and a second stage having a second output and comprising, a second two terminal logical network comprising at least one field effect transistor having a control electrode, the signal on said control electrode determining the impedance of an electrical path from one terminal to the other, a second field effect transistor means and second isolation field effect transistor means operable for simultaneously applying a voltage level to one terminal of said second logical network and to said second output during a third phase recurring clock signal, said second field effect transistor means operable only during said third phase recurring clock signal, second means for applying a different voltage level to the other terminal of said second logical network at least during a fourth recurring clock signal and said second isolation field effect transistor means operable for connecting said one terminal to said second output during said fourth phase recurring clock signal, said first recited output of the multiphase logical gating circuit comprising an input to a control electrode of said second two terminal logical network for forming one stage of a shift register.
Claim 2
Dependent Claim
363 words
A multiple phase logic gate for shift register stages comprising a first stage having an output, a two terminal logical network comprising at least one field effect transistor haVing a control electrode, the signal on said control electrode determining the impedance of an electrical path from one terminal to the other, field effect transistor means and isolation field effect transistor means operable to conduct electrical current therethrough to one terminal of said logical network and to said output for simultaneously applying a voltage level to said one terminal of said logical network and to said output during a first phase recurring clock signal, said field effect transistor means operable to conduct electrical current therethrough only during said first phase recurring clock signal, means for applying a different voltage level to the other terminal of said logical network at least during a second phase recurring clock signal, said isolation field effect transistor means operable to conduct electrical current therethrough during said second phase recurring clock signal for connecting said one terminal to said output during said second phase recurring clock signal, and a second stage having a second output and comprising, a second two terminal logical network comprising at least one field effect transistor having a control electrode, the signal on said control electrode determining the impedance of an electrical path from one terminal to the other, a second field effect transistor means and second isolation field effect transistor means operable for simultaneously applying a voltage level to one terminal of said second logical network and to said second output during a third phase recurring clock signal, said second field effect transistor means operable only during said third phase recurring clock signal, second means for applying a different voltage level to the other terminal of said second logical network at least during a fourth recurring clock signal and said second isolation field effect transistor means operable for connecting said one terminal to said second output during said fourth phase recurring clock signal, said first recited output of the multiphase logical gating circuit comprising an input to a control electrode of said second two terminal logical network for forming one stage of a shift register.
Claim 3
Dependent Claim
44 words
The combination recited in claim 1 wherein said first recited isolation field effect transistor means is connected between said first recited output and a common point between said first recited field effect transistor means and said one terminal of the two terminal logical network.
Claim 4
Dependent Claim
31 words
The combination recited in claim 2 wherein said second output is connected to a common point between said second field effect transistor means and said second isolation field effect transistor means.
Claim 5
Dependent Claim
42 words
The combination recited in claim 1 wherein said second isolation field effect transistor means is connected between said second output and a common point between said second field effect transistor means and said one terminal of said second two terminal logical network.
Claim 6
Dependent Claim
46 words
The combination recited in claim 4 wherein said first recited isolation field effect transistor means is connected between said first recited output and a common point between said first recited field effect transistor means and said one terminal of the first recited two terminal logical network.
Claim 7
Dependent Claim
86 words
A logic gate for use as a shift register stage having an output and comprising, first, second, and third field effect transistors connected in electrical series between means for providing a first and a second voltage level, and a fourth field effect transistor connected between said output and a common point between said first and second field effect transistor, said first, second and fourth field effect transistors being rendered conductive and nonconductive as a function of multiple phase clocking signals applied to their respective control electrodes.
Claim 8
Dependent Claim
86 words
A logic gate for use as a shift register stage having an output and comprising, first, second, and third field effect transistors connected in electrical series between means for providing a first and a second voltage level, and a fourth field effect transistor connected between said output and a common point between said first and second field effect transistor, said first, second and fourth field effect transistors being rendered conductive and nonconductive as a function of multiple phase clocking signals applied to their respective control electrodes.
Claim 9
Dependent Claim
129 words
The combination recited in claim 6 and further including a second logic gate having an output and comprising fifth and sixth field effect transistors in electrical seriEs, a two terminal logical network comprising at least one field effect transistor having a control electrode, the signal on the control electrode of the field effect transistor determining the impedance of an electrical path between the two terminals of the logical network, said fifth and sixth field effect transistors and said two terminal logical network being connected in electrical series between means for providing a first and a second voltage level, said output being connected to a common point between said fifth and sixth field effect transistors and providing an input signal to the control electrode of said third field effect transistor.
Claim 10
Dependent Claim
72 words
The combination recited in claim 6 and further including a second logic gate having an output and comprising fifth, sixth, and seventh field effect transistors in electrical series between means providing a first and a second voltage level, said second recited output connected at a common point between said fifth and sixth field effect transistors, said first recited output providing an input to the control electrode of said seventh field effect transistor.
Claim 11
Dependent Claim
132 words
A logic gate for use as a shift register stage having an output and comprising, first and second field effect transistors connected in electrical series, said output being connected at a common point between said first and second field effect transistors, a two terminal logical network comprising at least one field effect transistor having a control electrode, the signal on said control electrode determining the impedance between said two terminals, said two terminal logical network being connected in electrical series with said first and second field effect transistors between means providing a first and a second voltage level, a third field effect transistor connected in electrical series with the control electrode of one field effect transistor of said two terminal logical network for providing an input to said two terminal logical network.
Claim 12
Dependent Claim
132 words
A logic gate for use as a shift register stage having an output and comprising, first and second field effect transistors connected in electrical series, said output being connected at a common point between said first and second field effect transistors, a two terminal logical network comprising at least one field effect transistor having a control electrode, the signal on said control electrode determining the impedance between said two terminals, said two terminal logical network being connected in electrical series with said first and second field effect transistors between means providing a first and a second voltage level, a third field effect transistor connected in electrical series with the control electrode of one field effect transistor of said two terminal logical network for providing an input to said two terminal logical network.
Claim 13
Dependent Claim
122 words
The combination recited in claim 9 further including a second logic gate having an output and comprising a fourth field effect transistor, a second two terminal logical network comprising at least one field effect transistor, the signal on said field effect transistor determining the impedance between said two terminals, said two terminal logical network and said fourth field effect transistor being connected in electrical series between means providing a first and a second voltage level, said third field effect transistor being connected to a common point between said fourth field effect transistor and said second two terminal logical network whereby the output of said second logic gate is gated to said first logic gate when said third field effect transistor is conducting.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-23 | 1975-02-22 | 1975-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-23 | 1979-02-22 | 1979-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-23 | 1983-02-22 | 1983-08-24 | $7700.00 | Window Closed / Lapsed |