Signal generating circuit including a pair of cascade connected field effect transistors

Claim 2

A circuit comprising: a first and a second insulated gate field effect transistor each having two main electrodes and a control electrode, one main electrode of the first transistor being electrically connected to one main electrode of the second transistor; means coupled to the control electrode of the first transistor for biasing the first transistor in the saturated region of operation; means coupled to the control electrode and to the other main electrode of the second transistor, including a connection from the other main electrode of said first transistor to the control electrode of said second transistor, for biasing the second transistor in the linear region of operation with the resistance of the second transistor being controllable from said other main electrode of the first transistor.

Claim 3

The circuit according to claim 1 wherein said circuit is integrated on a single chip of semiconductive material and said first and second transistors are P channel MOS devices.

Claim 4

The circuit according to claim 1 further comprisIng: a capacitance means connected between the other main electrode of the first transistor and a point of reference potential; and switching means connected in shunt across said capacitance means, said switching means being periodically closed, whereby a ramp waveform is generated at the other main electrode of said first transistor.

Claim 5

The circuit according to claim 3 wherein said means for connecting the other main electrode of the first transistor to the control electrode of the second transistor comprises means for amplifying and means for filtering a signal appearing at the other main electrode of the first transistor.

Claim 6

The circuit according to claim 4 wherein said switching means comprises an N channel MOS device and said first and second transistors comprise P channel MOS devices, said switching means and said first and second transistors being integrated on the same semiconductor chip and further wherein said capacitance means is a discrete element external to said chip.

Claim 7

A ramp generator circuit comprising: first and second P channel MOS field effect transistors each having two main electrodes and a control electrode, one main electrode of the first transistor being electrically connected to one main electrode of the second transistor; biasing means connected to the control electrode of the first transistor for providing a biasing voltage having an amplitude of substantially twice the threshold voltage of said first transistor whereby said first transistor is operated in the saturated region; means coupled to the control electrode and to the other main electrode of said second transistor, including a connection from the other main electrode of said first transistor to the control electrode of said second transistor, for biasing the second transistor in the linear resistance region of operation with the resistance of the second transistor being controllable from said other main electrode of the first transistor; energy storage means connected between said other main electrode of the first transistor and a point of reference potential; a N channel MOS field effect transistor having a control electrode and two main electrodes, one main electrode of said N channel transistor being connected to said other main electrode of the first transistor, the other main electrode of said N channel transistor being connected to said point of reference potential; means for applying a periodic switching signal to the control electrode of said N channel transistor, a periodic ramp waveform thereby appearing at the other main electrode of said first P channel transistor; and output circuit means connected to the other main electrode of the first transistor.

Claim 8

A ramp generator circuit comprising: first and second P channel MOS field effect transistors each having two main electrodes and a control electrode, one main electrode of the first transistor being electrically connected to one main electrode of the second transistor; biasing means connected to the control electrode of the first transistor for providing a biasing voltage having an amplitude of substantially twice the threshold voltage of said first transistor whereby said first transistor is operated in the saturated region; means coupled to the control electrode and to the other main electrode of said second transistor, including a connection from the other main electrode of said first transistor to the control electrode of said second transistor, for biasing the second transistor in the linear resistance region of operation with the resistance of the second transistor being controllable from said other main electrode of the first transistor; energy storage means connected between said other main electrode of the first transistor and a point of reference potential; a N channel MOS field effect transistor having a control electrode and two main electrodes, one main electrode of said N channel transistor being connected to said other main electrode of the first transistor, the other main electrode of said N channel transistor being connected to said point of reference potential; means for applying a periodic switching signal to the control electrode of said N channel transistor, a periodic ramp waveform thereby appearing at the other main electrode of said first P channel transistor; and output circuit means connected to the other main electrode of the first transistor.