Sense amplifier for a memory device

Claim 2

A memory device, comprising memory cells and a sense amplifier for amplifying signals read out onto data input lines from the memory cells during a read cycle and outputting the amplified signals onto data output lines, wherein said sense amplifier comprises: a pair of transistors that respectively have complementary gate inputs that are connected to the data input lines to respond to the read out signals on the data input lines, and said pair of transistors further respectively having drain-source paths to provide complementary outputs connected to the data output lines so that the data output lines are separate from and directly unconnected with the data input lines; first and second load MOS transistors having gates respectively connected to the complementary outputs of said pair of transistors, and having the gates and drains being cross coupled at respective nodes that are connected to the complementary outputs to provide positive feedback; first switch means connected across said complementary outputs of said pair of transistors and being controlled by a first control signal; control means providing said first control signal to said first switch means; and in response to said first control signal, said first switch means is rendered conductive during beginning portion of the read cycle to minimize the potential difference of said complementary outputs and to dissolve the positive feedback operation of said first and second load MOS transistors and said first switch means is then rendered non-conductive.

Claim 3

A memory device according to claim 1, wherein said load MOS transistors are PMOS, and said pair of transistors are NMOS.

Claim 4

A memory device according to claim 1, wherein said load MOS transistors are NMOS, and said pair of transistors are PMOS.

Claim 5

A memory device according to claim 1, wherein said pair of transistors consist of third and fourth MOS transistors having a conduction type that is opposite to the conduction type of said first and second load MOS transistors.

Claim 6

A memory device according to claim 4, including a second switch means connected across the complementary inputs of said pair of transistors and controlled by a second control signal to minimize the potential difference of said complementary inputs; and control means providing the second control signal to said second switch means during the first portion of the sense portion of the read cycle.

Claim 7

A memory device according to claim 4, wherein said first switch means is a fifth PMOS transistor connected across said complementary outputs, and a sixth NMOS transistor connected in parallel with said fifth MOS transistor and across said complementary outputs.

Claim 8

A memory device according to claim 6, including a second switch means connected across the complementary inputs of said pair of transistors and controlled by a second control signal to minimize the potential difference of said complementary inputs; and control means providing the second control signal to said second switch means during the first portion of the sense portion of the read cycle.

Claim 9

A memory device according to claim 7, wherein said second switch means is a seventh PMOS transistor and an eighth NMOS transistor connected in parallel with each other across said complementary inputs.

Claim 10

A memory device according to claim 4, including a second switch means connected across the complementary inputs of said pair of transistors and controlled by a second control signal to minimize the potential difference of said complementary inputs; and control means providing the second control signal to said second switch means during the first portion of the sense portion of the read cycle; and wherein said control means provides said first control signal a substantial time after said second control signal.

Claim 11

A memory device according to claim 1, including a second switch means connected across the complementary inputs of said pair of transistors and controlled by a second control signal to minimize the potential difference of said complementary inputs; and control means providing the second control signal to said second switch means during the first portion of the sense portion of the read cycle.

Claim 12

A memory device according to claim 10, including a second switch means connected across the complementary inputs of said pair of transistors and controlled by a second control signal to minimize the potential difference of said complementary inputs; and control means providing the second control signal to said second switch means during the first portion of the sense portion of the read cycle; and wherein said control means provides said first control signal a substantial time after said second control signal.

Claim 13

A memory device according to claim 4, wherein said sense amplifier is serially connected with an additional sense amplifier to constitute a multi-stage sense amplifier circuit.

Claim 14

A memory device according to claim 12, wherein said additional sense amplifier is an all MOS circuit having differential transistors and current mirror load transistors, all connected to said data input lines before the first mentioned sense amplifier.

Claim 15

A memory device according to claim 1, wherein all of said transistors and said memory cells are constructed as a single chip integrated MOS transistor circuit.

Claim 16

A memory device according to claim 12, wherein the first stage of said multi-stage sense amplifier circuit is a sense preamplifier having means responsive to an amplifier control signal to reduce its amplification factor; and control means providing said amplifier control signal to said sense preamplifier for reducing the amplification factor of said sense preamplifier when the data outputs of said sense amplifier circuit reached a sufficient level to indicate the end of the sense portion of the read cycle.

Claim 17

A memory device according to claim 15, wherein said sense preamplifier means reduces the amplification factor to unity in response to the amplifier control signal.

Claim 18

A memory device according to claim 16, wherein said sense preamplifier is connected across the data input lines so that the sense preamplifier data inputs are directly connected to the sense preamplifier data outputs, and said sense preamplifier is completely turned off to draw no current in response to the amplifier control signal without interrupting the flow of data on the data input lines.

Claim 19

A memory device according to claim 1, wherein the sense amplifier is constructed with a load circuit consisting of two cross coupled load MOS transistors and a drive circuit consisting of two MOS differential transistors.

Claim 20

A memory device according to claim 18, including a MOS transistor having its drain and source connected in series with said differential and load transistors so that a control signal at its gate will activate and deactivate the sense amplifier and so that the sense amplifier consists of only five MOS transistors in addition to switch means equalizing the data output lines.

Claim 21

A memory device according to claim 1, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 22

A memory device according to claim 9, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 23

A memory device according to claim 13, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 24

A memory device according to claim 14, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 25

A memory device according to claim 15, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 26

A memory device according to claim 19, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 27

A memory device operable in a read cycle, comprising: data input lines: data output lines; memory cells connected to said data input lines; a preamplifier amplifying data signals read out from said memory cells onto said data input lines, said preamplifier having data inputs and data outputs; a sense amplifier amplifying output signals of said data outputs of said preamplifier, said sense amplifier having data inputs connected to the data input lines and data outputs connected to the data output lines, said sense amplifier data inputs being separate from and directly unconnected with said sense amplifier data outputs so that the data input lines and data output lines are not directly connected; said preamplifier and said sense amplifier constituting a sense amplifier circuit; said preamplifier including control means to reduce amplification at a fixed period of time after the start of the read cycle; and said preamplifier being directly connected across the data input lines so that said preamplifier data inputs are directly connected to said preamplifier data outputs.

Claim 28

A memory device operable in a read cycle, comprising: data input lines: data output lines; memory cells connected to said data input lines; a preamplifier amplifying data signals read out from said memory cells onto said data input lines, said preamplifier having data inputs and data outputs; a sense amplifier amplifying output signals of said data outputs of said preamplifier, said sense amplifier having data inputs connected to the data input lines and data outputs connected to the data output lines, said sense amplifier data inputs being separate from and directly unconnected with said sense amplifier data outputs so that the data input lines and data output lines are not directly connected; said preamplifier and said sense amplifier constituting a sense amplifier circuit; said preamplifier including control means to reduce amplification at a fixed period of time after the start of the read cycle; and said preamplifier being directly connected across the data input lines so that said preamplifier data inputs are directly connected to said preamplifier data outputs.

Claim 29

A memory device according to claim 26, including an additional sense amplifier serially connected with said preamplifier to constitute a multi-stage sense amplifier circuit.

Claim 30

A memory device according to claim 27, wherein said control means completely turns off said preamplifier to draw no current in response to the amplifier control signal without interrupting the flow of data on the data input lines.

Claim 31

A memory device according to claim 28, wherein all of said preamplifier, said sense amplifier and said memory cells are constructed as a single chip MOS integrated circuit.

Claim 32

A memory device according to claim 29, wherein said control means is responsive to a control signal to reduce said preamplifier amplification; and further comprising control means providing said control signal to said preamplifier when the data outputs of said sense amplifier circuit reach a sufficient level to indicate the end of the sense portion of the read cycle.

Claim 33

A memory device according to claim 30, wherein said control means reduced said preamplifier amplification to unity in response to its control signal.

Claim 34

A memory device according to claim 26, wherein all of said preamplifier, said sense amplifier and said memory cells are constructed as a single chip MOS integrated circuit.

Claim 35

A memory device according to claim 26, wherein said control means is responsive to a control signal to reduce said preamplifier amplification; and further comprising control means providing said control signal to said preamplifier when the data outputs of said sense amplifier circuit reach a sufficient level to indicate the end of the sense portion of the read cycle.

Claim 36

A memory device according to claim 33, wherein said control means reduces said preamplifier amplifications to unity in response to its control signal.

Claim 37

A memory device according to claim 34, wherein all of said preamplifier, said sense amplifier and said memory cells are constructed as a single chip MOS integrated circuit.

Claim 38

A memory device according to claim 33, wherein all of said preamplifier, said sense amplifier and said memory cells are constructed as a single chip MOS integrated circuit.

Claim 39

A memory device, comprising memory cells and a sense amplifier for amplifying signals read out onto data input lines from the memory cells during a read cycle and outputting the amplified signals onto data output lines, wherein said sense amplifier comprises: a pair of transistors that respectively have complementary gate inputs that are connected to the data input lines to respond to the read out signals on the data input lines, and said pair of transistors further respectively having drain-source paths to provide complementary outputs connected to the data output lines so that the data output lines are separate from and indirectly coupled through said transistors with said data input lines first and second load MOS transistors having gates respectively connected to the complementary outputs of said pair of transistors, and having the gates and drains being cross coupled at respective nodes that are connected to the complementary outputs to provide positive feedback; a first switch circuit connected across said complementary outputs of said pair of transistors and being controlled by a first control signal; control circuitry providing said first control signal to said first switch circuit; and in response to said first control signal, said first switch circuit being conductive during a beginning portion of the read cycle to minimize the potential difference of said complementary outputs and to dissolve the positive feedback operation of said first and second load MOS transistors and said first switch circuit is then rendered non-conductive.

Claim 40

A memory device, comprising memory cells and a sense amplifier for amplifying signals read out onto data input lines from the memory cells during a read cycle and outputting the amplified signals onto data output lines, wherein said sense amplifier comprises: a pair of transistors that respectively have complementary gate inputs that are connected to the data input lines to respond to the read out signals on the data input lines, and said pair of transistors further respectively having drain-source paths to provide complementary outputs connected to the data output lines so that the data output lines are separate from and indirectly coupled through said transistors with said data input lines first and second load MOS transistors having gates respectively connected to the complementary outputs of said pair of transistors, and having the gates and drains being cross coupled at respective nodes that are connected to the complementary outputs to provide positive feedback; a first switch circuit connected across said complementary outputs of said pair of transistors and being controlled by a first control signal; control circuitry providing said first control signal to said first switch circuit; and in response to said first control signal, said first switch circuit being conductive during a beginning portion of the read cycle to minimize the potential difference of said complementary outputs and to dissolve the positive feedback operation of said first and second load MOS transistors and said first switch circuit is then rendered non-conductive.

Claim 41

A memory device according to claim 37, wherein said load MOS transistors are PMOS, and said pair of transistors are NMOS.

Claim 42

A memory device according to claim 37, wherein said pair of transistors consist of third and fourth MOS transistors having a conduction type that is opposite to the conduction type of said first and second load MOS transistors.

Claim 43

A memory device according to claim 39, including a second switch circuit connected across the complementary inputs of said pair of transistors and controlled in conductivity by a second control signal; and said control circuitry providing the second control signal to said second switch circuit during the beginning of the read cycle.

Claim 44

A memory device according to claim 39, wherein said first switch circuit is a fifth PMOS transistor connected across said complementary outputs, and a sixth NMOS transistor connected in parallel with said firth PMOS transistor and across said complementary outputs.

Claim 45

A memory device according to claim 41, including a second switch circuit connected across the complementary inputs of said pair of transistors and controlled by a second control signal; and said control circuitry providing the second control signal to said second switch circuit during beginning of the read cycle.

Claim 46

A memory device according to claim 42, wherein said second switch circuit is a seventh PMOS transistor and an eighth NMOS transistor connected in parallel with each other across said complementary inputs.

Claim 47

A memory device according to claim 39, including a second switch circuit connected across the complementary inputs of said pair of transistors and controlled by a second control signal; and said control circuitry providing the second signal to said second switch circuit during the beginning of the read cycle; and wherein said control circuitry provides said first control signal a substantial time after said second control signal.

Claim 48

A memory device according to claim 37, including a second switch circuit connected across the complementary inputs of said pair of transistors and controlled by a second control signal; and said control circuitry providing the second control signal to said second switch circuit during the beginning of the read cycle.

Claim 49

A memory device according to claim 37, including a second switch circuit connected across the complementary inputs of said pair of transistors and controlled by a second control signal; and said control circuitry providing the second control signal to said second switch circuit during the beginning of the read cycle; and wherein said control circuitry provides said first control signal a substantial time after said second control signal.

Claim 50

A memory device according to claim 39, wherein said sense amplifier is serially connected with an additional sense amplifier to constitute a multi-stage sense amplifier.

Claim 51

A memory device according to claim 47, wherein said additional sense amplifier is an all MOS circuit having differential transistors and current mirror load transistors, all connected to said data input lines before the first mentioned sense amplifier.

Claim 52

A memory device according to claim 37, wherein all of said transistors and said memory cells are constructed as a single chip integrated MOS transistor circuit.

Claim 53

A memory device according to claim 47, wherein the first stage of said multi-stage sense amplifier is a sense preamplifier responsive to an amplifier control signal to reduce its amplification factor; and including control circuitry providing said amplifier control signal to said sense preamplifier for reducing the amplification factor of said sense preamplifier when the data outputs of said sense amplifier circuit reached a sufficient level to indicate the end of the sense portion of the read cycle.

Claim 54

A memory device according to claim 50, wherein said sense preamplifier reduces the amplification factor to unity in response to the amplifier control signal.

Claim 55

A memory device according to claim 51, wherein said sense preamplifier is connected across the data input lines so that the sense preamplifier data inputs are directly connected to the sense preamplifier data outputs, and said sense preamplifier completely turns off to draw no current in response to the amplifier control signal without interrupting the flow of data on the data input lines.

Claim 56

A memory device according to claim 37, wherein the sense amplifier is constructed with a load circuit consisting of two cross coupled load MOS transistors and a drive circuit consisting of two MOS differential transistors.

Claim 57

A memory device according to claim 53, including a MOS transistor having its drain and source connected in series with said differential and load transistors so that a control signal at its gate will activate and deactivate the sense amplifier and so that the sense amplifier consists of only five MOS transistors in addition to switch circuit equalizing the data lines.

Claim 58

A memory device according to claim 37, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 59

A memory device according to claim 44, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 60

A memory device according to claim 48, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 61

A memory device according to claim 49, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 62

A memory device according to claim 50, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 63

A memory device according to claim 54, wherein said data input lines are complimentary for each memory cell and sense amplifier.

Claim 64

A memory device operable in a read cycle, comprising: data input lines: data output lines; memory cells connected to said data lines; a preamplifier amplifying data signals read out from said memory cells onto said data lines, said preamplifier having data inputs and data outputs; a sense amplifier amplifying output signals of said data outputs of said preamplifier, said sense amplifier having data inputs connected to the data input lines and data outputs connected to the data output lines, said sense amplifier data inputs being separate from and directly unconnected with said sense amplifier data outputs so that the data input lines and data output lines are not directly connected; said preamplifier and said sense amplifier constituting a sense amplifier circuit; said preamplifier including control circuitry to reduce amplification at a fixed period of time after the start of the read cycle; and said preamplifier being directly connected across the data lines so that said preamplifier data inputs are directly connected to said preamplifier data outputs.

Claim 65

A memory device operable in a read cycle, comprising: data input lines: data output lines; memory cells connected to said data lines; a preamplifier amplifying data signals read out from said memory cells onto said data lines, said preamplifier having data inputs and data outputs; a sense amplifier amplifying output signals of said data outputs of said preamplifier, said sense amplifier having data inputs connected to the data input lines and data outputs connected to the data output lines, said sense amplifier data inputs being separate from and directly unconnected with said sense amplifier data outputs so that the data input lines and data output lines are not directly connected; said preamplifier and said sense amplifier constituting a sense amplifier circuit; said preamplifier including control circuitry to reduce amplification at a fixed period of time after the start of the read cycle; and said preamplifier being directly connected across the data lines so that said preamplifier data inputs are directly connected to said preamplifier data outputs.

Claim 66

A memory device according to claim 61, including an additional sense amplifier serially connected with said preamplifier to constitute a multi-stage sense amplifier circuit.

Claim 67

A memory device according to claim 62, wherein said control circuitry completely turns off said preamplifier to draw no current in response to the amplifier control signal without interrupting the flow of data on the data input lines.

Claim 68

A memory device according to claim 63, wherein all of said preamplifier, said sense amplifier and said memory cells are constructed as a single chip MOS integrated circuit.

Claim 69

A memory device according to claim 64, wherein said control circuitry is responsive to a control signal to reduce said preamplifier amplification; and further comprising control circuitry providing said control signal to said preamplifier when the data outputs of said sense amplifier circuit reach a sufficient level to indicate the end of the sense portion of the read cycle.

Claim 70

A memory device according to claim 65, wherein said control circuitry reduces said preamplifier amplification to unity in response to its control signal.

Claim 71

A memory device according to claim 61, wherein all of said preamplifier, said sense amplifier and said memory cells are constructed as a single chip MOS integrated circuit.

Claim 72

A memory device according to claim 61, wherein said control circuitry is responsive to a control signal to reduce said preamplifier amplification; and further comprising control circuitry providing said control signal to said preamplifier when the data outputs of said sense amplifier circuit reach a sufficient level to indicate the end of the sense portion of the read cycle.

Claim 73

A memory device according to claim 68, wherein said control circuitry reduces said preamplifier amplification to unity in response to its control signal.

Claim 74

A memory device according to claim 69, wherein all of said preamplifier, said sense amplifier and said memory cells are constructed as a single chip MOS integrated circuit.

Claim 75

A memory device according to claim 68, wherein all of said preamplifier, said sense amplifier and said memory cells are constructed as a single chip MOS integrated circuit.