US5023841A
Expired / Lapsed
US
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Double stage sense amplifier for random access memories
Assignee: International Business Machines Corp
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Filing: 1989-02-21
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Granted: 1991-06-11
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Expires: 2009-02-21
Abstract
Abstract In combination with an electronic memory of the type having a plurality of memory cells (CA, . . . CN) connected between two bit lines (BLT, BLC) having inherent bit line capacitances (C1, C2), there is disclosed an improved sense amplifier (15) comprised of two stages. A first stage (16) includes a first clocked latch (5) having an enable device (T5), gated by a first control signal (SSA) and bit switches (T6, T7) connected between the common nodes (6, 7) of said first clocked latch and said bit lines, and gated by a bit switch control signal (BS) to provide an output signal on first data lines (DLT, DLC). A second stage (17) includes a second clocked latch (20) having an enable device (T24) gated by a second signal (SL) and data switches (T28, T29) connected between second data lines (DT, DC) at the same potential as data output nodes (21, 22) of said second clocked latch and said first data lines (DLT, DLC). Said data switches (T28, T29) are gated by a data switch control signal (DS) which is derived from the bit switch control signal (BS), so that the first and second stages (16, 17) operate sequentially to amplify the data continuously along the sensing chain of the data path during a READ operation to provide a data output signal on said data output nodes. The data is then available for further processing at the output terminal (24) of the output driver (23).
Inventors
- 👤 Chekib Akrout
- 👤 Pierre Coppens
- 👤 Bernard Denis
- 👤 Pierre-Yves Urena
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:42
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
141 words
A sense amplifier for amplifying the difference between first and second signals on respective first and second signal lines, each said first and second signal line having inherent signal line capacitance, said sense amplifier comprising: first amplifying means responsive to said first and second signals for providing a first differential output signal, including a first clocked latch, and first switching means for selectively connecting said first clocked latch to said first and second signal lines; a second amplifying means responsive to said first differential output signal, including a second clocked latch, and second switching means for selecting said first clocked latch from a plurality of first clocked latches and connecting said second clocked latch to said selected first clocked latch; and means for controlling said first and second amplifying means to sequentially amplify the difference between said first and second signals.
Claim 2
Dependent Claim
141 words
A sense amplifier for amplifying the difference between first and second signals on respective first and second signal lines, each said first and second signal line having inherent signal line capacitance, said sense amplifier comprising: first amplifying means responsive to said first and second signals for providing a first differential output signal, including a first clocked latch, and first switching means for selectively connecting said first clocked latch to said first and second signal lines; a second amplifying means responsive to said first differential output signal, including a second clocked latch, and second switching means for selecting said first clocked latch from a plurality of first clocked latches and connecting said second clocked latch to said selected first clocked latch; and means for controlling said first and second amplifying means to sequentially amplify the difference between said first and second signals.
Claim 3
Dependent Claim
32 words
The sense amplifier of claim 1 wherein said controlling means includes: means for sequentially actuating said first and second switching means; and means for sequentially actuating said first and second clocked latches.
Claim 4
Dependent Claim
65 words
The sense amplifier of claim 2 wherein each of said first and second clocked latches comprises: a first pair of cross-coupled field-effect transistors connected to a first bias potential; a second pair of cross-coupled field-effect transistors connected to said first pair of cross-coupled field-effect transistors; and an enabling field-effect transistor connected between said second pair of cross-coupled field effect transistors and a second bias potential.
Claim 5
Dependent Claim
49 words
The sense amplifier of claim 3 wherein: said first switching means includes a pair of field-effect transistors connected between said first clocked latch and said signal lines; and said second switching means includes a pair of field-effect transistors connected between said second clocked latch and said first clocked latch.
Claim 6
Dependent Claim
29 words
The sense amplifier of claim 3 wherein said first amplifying means further includes restore means for selectively raising the outputs of said first clocked latch to a high voltage.
Claim 7
Dependent Claim
25 words
The sense amplifier of claim 5 wherein said restore means includes a pair of field-effect transistors connected between said first latch and a bias potential.
Claim 8
Dependent Claim
29 words
The sense amplifier of claim 3 wherein said second amplifying means further includes restore means for selectively raising the outputs of said second clocked latch to a high voltage.
Claim 9
Dependent Claim
25 words
The sense amplifier of claim 7 wherein said restore means includes a pair of field-effect transistors connected between said first latch and a bias potential.
Claim 10
Dependent Claim
25 words
The sense amplifier of claim 3 wherein said second amplifying means further include means for equalizing the signals at the outputs of said second latch.
Claim 11
Dependent Claim
22 words
The sense amplifier of claim 3 wherein said first amplifying means further include means for writing data into said first clocked latch.
Claim 12
Dependent Claim
24 words
The sense amplifier of claim 1 wherein said first and second clocked latches are each biased between a high and a low power supply.
Claim 13
Dependent Claim
21 words
The sense amplifier of claim 1 and further including a signal driver connected to the output of said second clocked latch.
Claim 14
Dependent Claim
27 words
The sense amplifier of claim 1 wherein said first and second signal lines comprise first and second bit lines, respectively, connected to a plurality of memory cells.
Claim 15
Independent Claim
155 words
A method for amplifying a difference signal between first and second signal lines, respectively, said first and second signal lines having an inherent signal line capacitance, said method comprising the steps of: selecting said first and second signal lines from a plurality of signal lines; transferring said difference signal from said selected first and second signal lines to a first clocked latch; clocking said first clocked latch when said difference signal has reached a value sufficient such that said difference signal is amplified and stored in said first clocked latch; selecting said first clocked latch from a plurality of first clocked latches transferring the amplified and stored difference signal from said selected first clocked latch to a second clocked latch; and clocking said second clocked latch when the amplified and stored difference signal has reached a value sufficient such that the amplified and stored signal is further amplified and stored in said second clocked latch.
Claim 16
Independent Claim
155 words
A method for amplifying a difference signal between first and second signal lines, respectively, said first and second signal lines having an inherent signal line capacitance, said method comprising the steps of: selecting said first and second signal lines from a plurality of signal lines; transferring said difference signal from said selected first and second signal lines to a first clocked latch; clocking said first clocked latch when said difference signal has reached a value sufficient such that said difference signal is amplified and stored in said first clocked latch; selecting said first clocked latch from a plurality of first clocked latches transferring the amplified and stored difference signal from said selected first clocked latch to a second clocked latch; and clocking said second clocked latch when the amplified and stored difference signal has reached a value sufficient such that the amplified and stored signal is further amplified and stored in said second clocked latch.
Claim 17
Dependent Claim
23 words
A method in accordance with claim 14 wherein each of said transferring steps includes the steps of turning on a pair of transistors.
Claim 18
Dependent Claim
66 words
A method in accordance with claim 14 wherein each of said first and second clocked latches comprises: a first pair of cross-coupled field-effect transistors connected to a first bias potential; a second pair of cross-coupled field-effect transistors connected to said first pair of cross-coupled field-effect transistors; and an enabling field-effect transistor connected between said second pair of cross-coupled field effect transistors and a second bias potential.
Claim 19
Dependent Claim
24 words
A method in accordance with claim 14 wherein said first and second signal lines comprise bit lines connected to a plurality of memory cells.
References Cited (Backward Citations)
US3600609A
Cited
US3879621A
Cited
US4193127A
Cited
US4658158A
Cited
US4616342A
Cited
WO1985002314A2
Cited
US4542483A
Cited
EP0170285A2
Cited
US4764901A
Cited
US4555777A
Cited
US4656371A
Cited
US4719596A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-10 | 1994-12-10 | 1995-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-10 | 1998-12-10 | 1999-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-10 | 2002-12-10 | 2003-06-11 | $7700.00 | Window Closed / Lapsed |