US3600609A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Igfet read amplifier for double-rail memory systems
Assignee: Shell USA Inc
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Filing: 1970-02-03
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Granted: 1971-08-17
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Expires: 1990-02-03
Abstract
Abstract A pair of cross-coupled IGFET devices connected in a race mode are combined with IGFET inverters to convert a differential double-rail output of an IGFET memory circuit into a full-logiclevel double-rail data output.
Inventors
- 👤 Alton O Christensen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/00; G11C7/06; G11C7/065; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356026
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
107 words
An IGFET read amplifier for converting a double-rail differential memory output signal to a full-logic output signal, comprising: a. a source of first clock pulses; b. a pair of cross-coupled IGFET means each having a sourcedrain circuit connected between a node and said source of first clock pulses, and a gate electrode connected to the node of the opposite IGFET means; c. means for applying a double-rail differential signal to said nodes; and d. level-converting means having data input means connected to one of said nodes; e. the output of said level-converting means being at full logic level and constituting the full-logic output signal of said amplifier.
Claim 2
Dependent Claim
107 words
An IGFET read amplifier for converting a double-rail differential memory output signal to a full-logic output signal, comprising: a. a source of first clock pulses; b. a pair of cross-coupled IGFET means each having a sourcedrain circuit connected between a node and said source of first clock pulses, and a gate electrode connected to the node of the opposite IGFET means; c. means for applying a double-rail differential signal to said nodes; and d. level-converting means having data input means connected to one of said nodes; e. the output of said level-converting means being at full logic level and constituting the full-logic output signal of said amplifier.
Claim 3
Dependent Claim
29 words
The amplifier of claim 1, in which said level-converting means is a ratioless IGFET inverter, and said data input means is the data gate electrode of said IGFET inverter.
Claim 4
Dependent Claim
15 words
The amplifier of claim 2, in which said inverter is powered by second clock pulses.
Claim 5
Dependent Claim
24 words
The amplifier of claim 3, in which said second clock pulses have the same onset but a longer duration than said first clock pulses.
Claim 6
Dependent Claim
43 words
The amplifier of claim 1, in which said signal-applying means include double-rail signal gate means connected between a source of double-rail differential signals and said nodes; and means for enabling said signal gate means simultaneously with the presence of said first clock pulses.
Claim 7
Dependent Claim
36 words
The amplifier of claim 1, in which said level-converting means include a pair of ratioless IGFET inverters, one connected to each of said nodes, to produce a full-logic-level double-rail output at the outputs of said inverters.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-16 | 1975-02-15 | 1975-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-16 | 1979-02-15 | 1979-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-16 | 1983-02-15 | 1983-08-17 | $7700.00 | Window Closed / Lapsed |