Semiconductor memory device

Claim 2

A semiconductor memory device comprising: decoding means (12) for generating a decode signal in accordance with an address signal; memory means including a plurality of memory cells (Mll, M21, ...) which are selectively actuated by said decode signal; and transfer means (28, BAll, BB11), connected to said memory cells (Mll, M21, ...), for transferring data to and from the actuated one of the memory cells (Mll, M21, ...), characterized by further comprising latching means (Lll, SAll, SB11) for latching the data on said transfer means (28, BAll, BB11), and control means (26) for detecting the update of the address signal and permitting said latching means (Lll, SAll, SB11) to latch and hold the data for a predetermined period after the update of the address signal.

Claim 3

A semiconductor memory device according to claim 1, characterized in that said transfer means includes a precharge circuit (28) and a pair of bit lines (BAll, BB11) which are precharged by said precharge circuit (28) and whose potentials vary in accordance with the data stored in the actuated memory cell.

Claim 4

A semiconductor memory device according to claim 2, characterized in that said transfer means further includes a sense amplifier (AX11) which senses the potential difference between the bit lines (BAll, BB11) and sets the bit lines (BAll, BB11) to predetermined potentials corresponding to the difference.

Claim 5

A semiconductor memory device according to claim 3, characterized in that said latching means includes transfer gates (SA11, SB11) which turn on in response to a first control signal (φ1) and a latching circuit (Lll) which is connected to said bit lines (BAll, BB11) through the respective transfer gates (SAll, SB11) and latches the potentials on said first and second bit lines (BAll, BB11) in response to a second control signal (LE), said control means includes a timing controller (26) which generates, in response to the update of said address signal, said first control signal (φ1) for a predetermined period, and said second control signal (LE) during said transfer gates (SAll, SB11) are conductive.

Claim 6

A semiconductor memory device according to claim 4, characterized in that said memory device is further provided with second transfer means (30, BX1, BYI) for transferring the data held in said latching means.

Claim 7

A semiconductor memory device according to claim 5, characterized in that said timing controller (26) further generates a third control signal ( f 2) after the first transfer gates (SAll, SB11) are turned off, said latching means further includes second transfer gates (SC11, SD11) which turn on in response to the third control signal (φ2), and said second transfer means includes a second precharge circuit (30) and a second pair of bit lines (BXl, BYl) which are connected to said latching circuit (11) through the respective bit lines (BAll, BB11) and vary in accordance with the latched data.

Claim 8

A semiconductor memory device according to claim 6, characterized in that said memory cells (Mll, M21, ...) are of a dynamic type.

Claim 9

A semiconductor memory device according to claim 6, characterized in that said memory cells (M11, M21, ...) are of a static type.

Claim 10

A semiconductor memory device according to claim 7, characterized in that said memory device is further provided with refresh means (24, 20) for periodically generating a refresh address signal, and multiplex means (18) for receiving the first address signal and supplying a selected one of the first address signal to said decoding means (12), said timing controller (26) further permits said multiplex means to supply said first address signal in response to the update of the first address signal and permits it to supply said refresh address signal after a predetermined period has elapsed from the update of the first address signal.

Claim 11

A semiconductor memory device comprising: first decoding means (12) for generating a first decode signal in accordance with a first address signal; second decoding means (14) for generating a second decode signal in accordance with a second address signal; a plurality of memory blocks (MB11, MB12, ...) each including a plurality of memory cells which are selectively actuated by said first decode signal; and transfer means (28, ...; BA11, BB11; BAI2, BB12; ...), connected to said memory cells in each memory block, for transferring data to and from the actuated one of the memory cells in each memory block, characterized by further comprising latching means (Lll; S11, S12, ...) for selectively latching the data on said transfer means (28, ...; BAll, BB11; BA12, BB12; ...), and control means (26) for detecting the update of at least one of the first and second address signals and permitting said latching means (Lll; S11, S12, ...) to latch and hold the data of the selected one memory block by the second decode signal for a predetermined period after said update of at least one of the address signals.

Claim 12

A semiconductor memory device comprising: first decoding means (12) for generating a first decode signal in accordance with a first address signal; second decoding means (14) for generating a second decode signal in accordance with a second address signal; a plurality of memory blocks (MB11, MB12, ...) each including a plurality of memory cells which are selectively actuated by said first decode signal; and transfer means (28, ...; BA11, BB11; BAI2, BB12; ...), connected to said memory cells in each memory block, for transferring data to and from the actuated one of the memory cells in each memory block, characterized by further comprising latching means (Lll; S11, S12, ...) for selectively latching the data on said transfer means (28, ...; BAll, BB11; BA12, BB12; ...), and control means (26) for detecting the update of at least one of the first and second address signals and permitting said latching means (Lll; S11, S12, ...) to latch and hold the data of the selected one memory block by the second decode signal for a predetermined period after said update of at least one of the address signals.