CMOS output circuit compensating for back-gate bias effects

Claim 2

An output circuit comprising: an input terminal; first and second MOS transistors of a same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to an input signal from said input terminal, a level of said first power supply being higher than a level of said second power supply; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistor having a first terminal connected to said output terminal and a second terminal connected to a back gate of said first MOS transistor, wherein a fixed potential is applied to a gate of said third MOS transistor; and a fourth MOS transistor having a first terminal connected to said back gate of said first MOS transistor and a second terminal connected to a fixed potential, and said fourth MOS transistor being turned on in response to the input signal and making a level of a back gate of said first MOS transistor equal to the level of said second power supply, thereby reliably turning off said first MOS transistor.

Claim 3

An output circuit comprising: an input terminal; an output terminal; a first MOS transistor of a first conductivity type having a first terminal connected to a first potential, and turned on in response to a first input signal; a second MOS transistor of a second conductivity type having a first terminal connected to a second terminal of said first MOS transistor and a second terminal connected to said output terminal, and a gate connected to the first potential, said second MOS transistor preventing a high-level signal supplied to said output terminal from being transferred to said second terminal of said first MOS transistor; a third MOS transistor of the second conductivity type having a first terminal connected to said output terminal and a second terminal connected to a second potential, and turned on in response to a second input signal; a fourth MOS transistor of the second conductivity type having a first terminal connected to a back gate of said second MOS transistor and a second terminal connected to said output terminal, and turned on in response to a third input signal; and a fifth MOS transistor having a a first terminal connected to said back gate of said second MOS transistor and a second terminal connected to the second potential, and turned on in response to a fourth input signal.

Claim 4

An output circuit comprising: an input terminal; an output terminal; a first MOS transistor of a first conductivity type having a first terminal connected to a first potential, and turned on in response to a first input signal; a second MOS transistor of a second conductivity type having a first terminal connected to a second terminal of said first MOS transistor and a second terminal connected to said output terminal, and a gate connected to the first potential, said second MOS transistor preventing a high-level signal supplied to said output terminal from being transferred to said second terminal of said first MOS transistor; a third MOS transistor of the second conductivity type having a first terminal connected to said output terminal and a second terminal connected to a second potential, and turned on in response to a second input signal; a fourth MOS transistor of the second conductivity type having a first terminal connected to a back gate of said second MOS transistor and a second terminal connected to said output terminal, and turned on in response to a third input signal; and a fifth MOS transistor having a a first terminal connected to said back gate of said second MOS transistor and a second terminal connected to the second potential, and turned on in response to a fourth input signal.

Claim 5

The output circuit according to claim 2, wherein a back gate of said fourth MOS transistor is connected to the second potential.

Claim 6

The output circuit according to claim 2, wherein a back gate of said fourth MOS transistor is connected to the output terminal.

Claim 7

An output circuit comprising: an input terminal; a disable signal input terminal; a control signal generating circuit for generating first and second control signals upon receipt of an input signal and a disable signal from said input terminal and said disable signal input terminal; first and second MOS transistors of the same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to the first and second control signals; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistor of the same conductivity type as said first and second MOS transistors, said third MOS transistor having one terminal connected to a back gate of said first MOS transistor, a gate which receives said first control signal, and a back gate connected to said second power supply; a fourth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the input signal and a back gate connected to said second power supply; and a fifth MOS transistor of the same conductivity type as said first and second MOS transistors, said fifth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the disable signal and a back gate connected to said second power supply.

Claim 8

An output circuit comprising: an input terminal; a disable signal input terminal; a control signal generating circuit for generating first and second control signals upon receipt of an input signal and a disable signal from said input terminal and said disable signal input terminal; first and second MOS transistors of the same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to the first and second control signals; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistor of the same conductivity type as said first and second MOS transistors, said third MOS transistor having one terminal connected to a back gate of said first MOS transistor, a gate which receives said first control signal, and a back gate connected to said second power supply; a fourth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the input signal and a back gate connected to said second power supply; and a fifth MOS transistor of the same conductivity type as said first and second MOS transistors, said fifth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the disable signal and a back gate connected to said second power supply.

Claim 9

An output according to claim 5, wherein said control signal generating circuit generates the first and second control signals making said output terminal enter a high-impedance state when the disable signal is maintained at a first level.

Claim 10

An output circuit according to claim 6, wherein said first and second control signals are maintained at a second level when the disable signal is at the first level.

Claim 11

An output circuit comprising: an input terminal; a disable signal input terminal; a control signal generating circuit for generating first and second control signals upon receipt of an input signal and a disable signal from said input terminal and said disable signal input terminal; first and second MOS transistors of the same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to the first and second control signals; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistor of the same conductivity type as said first and second MOS transistors, said third MOS transistor having one terminal connected to a back gate of said first MOS transistor, a gate which receives said first control signal and a back gate connected to the back gate of said first MOS transistor; a fourth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the input signal, and a back gate connected to said second power supply; and a fifth MOS transistor of the same conductivity type as said first and second MOS transistors, said fifth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the disable signal and a back gate connected to said second power supply.

Claim 12

An output circuit comprising: an input terminal; a disable signal input terminal; a control signal generating circuit for generating first and second control signals upon receipt of an input signal and a disable signal from said input terminal and said disable signal input terminal; first and second MOS transistors of the same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to the first and second control signals; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistor of the same conductivity type as said first and second MOS transistors, said third MOS transistor having one terminal connected to a back gate of said first MOS transistor, a gate which receives said first control signal and a back gate connected to the back gate of said first MOS transistor; a fourth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the input signal, and a back gate connected to said second power supply; and a fifth MOS transistor of the same conductivity type as said first and second MOS transistors, said fifth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the disable signal and a back gate connected to said second power supply.

Claim 13

An output circuit according to claim 8, wherein said control signal generating circuit generates the first and second control signals making said output terminal enter a high-impedance state when the disable signal is maintained at a first level.

Claim 14

An output circuit according to claim 9, wherein the first and second control signals are maintained at a second level when the disable signal is at the first level.

Claim 15

An output circuit comprising: an input terminal; a disable signal input terminal a control signal generating circuit for generating first and second control signals upon receipt of an input signal and a disable signal from said input terminal and said disable signal input terminal; first and second MOS transistors of the same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to the first and second control signals; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistors of the same conductivity type as said first and second MOS transistors, said third MOS transistor having one terminal connected to a back gate of said first MOS transistor, a gate which receives the first control signal, and a back gate connected to said second power supply; a fourth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving said second control signal and a back gate connected to said second power supply; and a fifth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, and a second terminal connected to the back gate of said first MOS .transistor, a gate for receiving the disable signal and a back gate connected to said second power supply.

Claim 16

An output circuit comprising: an input terminal; a disable signal input terminal a control signal generating circuit for generating first and second control signals upon receipt of an input signal and a disable signal from said input terminal and said disable signal input terminal; first and second MOS transistors of the same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to the first and second control signals; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistors of the same conductivity type as said first and second MOS transistors, said third MOS transistor having one terminal connected to a back gate of said first MOS transistor, a gate which receives the first control signal, and a back gate connected to said second power supply; a fourth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving said second control signal and a back gate connected to said second power supply; and a fifth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, and a second terminal connected to the back gate of said first MOS .transistor, a gate for receiving the disable signal and a back gate connected to said second power supply.

Claim 17

An output circuit according to claim 11, wherein said control signal generating circuit generates the first and second control signals making said output terminal enter a high-impedance state when the disable signal is maintained at a first level.

Claim 18

An output circuit according to claim 12, wherein said first and second control signals are maintained at a second level when the disable signal is at the first level.

Claim 19

An output circuit comprising: an input terminal; a disable signal input terminal; a control signal generating circuit for generating first and second control signals upon receipt of an input signal and a disable signal from said input terminal and said disable signal input terminal; first and second MOS transistors of the same conductivity type connected in series between first and second power supplies to form a current path, and alternatively turned on in response to the first and second control signals; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistor of the same conductivity type as said first and second MOS transistors, said third MOS transistor having one terminal connected to a back gate of said first MOS transistor, a gate which receives the first control signal and a back gate connected to the back gate of said first MOS transistor; a fourth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the second control signal, and a back gate connected to said second power supply; and a fifth MOS transistor of the same conductivity type as said first and second MOS transistors, said fifth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the disable signal and a back gate connected to said second power supply.

Claim 20

An output circuit comprising: an input terminal; a disable signal input terminal; a control signal generating circuit for generating first and second control signals upon receipt of an input signal and a disable signal from said input terminal and said disable signal input terminal; first and second MOS transistors of the same conductivity type connected in series between first and second power supplies to form a current path, and alternatively turned on in response to the first and second control signals; an output terminal connected to a connection point between said first and second MOS transistors; a third MOS transistor of the same conductivity type as said first and second MOS transistors, said third MOS transistor having one terminal connected to a back gate of said first MOS transistor, a gate which receives the first control signal and a back gate connected to the back gate of said first MOS transistor; a fourth MOS transistor of the same conductivity type as said first and second MOS transistors, said fourth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the second control signal, and a back gate connected to said second power supply; and a fifth MOS transistor of the same conductivity type as said first and second MOS transistors, said fifth MOS transistor having a first terminal connected to said second power supply, a second terminal connected to the back gate of said first MOS transistor, a gate for receiving the disable signal and a back gate connected to said second power supply.

Claim 21

An output circuit according to claim 14, wherein said control signal generating circuit generates the first and second control signals making said output terminal enter a high-impedance state when the disable signal is maintained at a first level.

Claim 22

An output circuit according to claim 15, wherein said first and second control signals are maintained at a second level when the disable signal is at the first level.