US4959563A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Adjustable low noise output circuit
Assignee: Texas Instruments Inc
•
Filing: 1988-06-29
•
Granted: 1990-09-25
•
Expires: 2008-06-29
Abstract
Abstract An output circuit is provided which contains voltage control circuitry (14) which drives the gates of the output transistors (18,20) such that the change in current remains relatively constant. The desired voltage output of the voltage control circuitry (14) can be implemented for a CMOS device using N channel and P channel transistors having their gates connected to V cc and ground respectively. The amount of current control may be adjusted to compensate for environmental conditions such as temperature or voltage supply either dynamically or prior to use.
Inventors
- 👤 Stephen R. Schenck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
223 words
Output circuitry to reduce inductive voltage spikes in an integrated circuit comprising: an input node for receiving an input voltage signal; an output transistor having first, second and control terminals; voltage control circuitry responsive to the voltage at said input node for controlling the voltage of the control terminal of said output transistor with respect to time such that the change in output current between the first and second terminals with respect to time has a relatively constant magnitude and; magnitude control circuitry connected to said voltage control circuitry for controlling the magnitude of constant change of output current with respect to time; wherein said output transistor comprises an N channel output transistor and said voltage control circuitry comprises: a first P channel transistor having its gate connected to said input node, a first terminal connected to a predetermined high voltage and a second terminal connected to a first node; an N channel transistor having a gate connected to said input node, a first terminal connected to a predetermined low voltage and a second terminal connected to the gate of said output transistor; and a plurality of P channel transistors each having gates selectively connected to a respective predetermined voltage and each having first and second terminals connected between the second terminal of said first P channel transistor and said N channel transistor.
Claim 2
Dependent Claim
223 words
Output circuitry to reduce inductive voltage spikes in an integrated circuit comprising: an input node for receiving an input voltage signal; an output transistor having first, second and control terminals; voltage control circuitry responsive to the voltage at said input node for controlling the voltage of the control terminal of said output transistor with respect to time such that the change in output current between the first and second terminals with respect to time has a relatively constant magnitude and; magnitude control circuitry connected to said voltage control circuitry for controlling the magnitude of constant change of output current with respect to time; wherein said output transistor comprises an N channel output transistor and said voltage control circuitry comprises: a first P channel transistor having its gate connected to said input node, a first terminal connected to a predetermined high voltage and a second terminal connected to a first node; an N channel transistor having a gate connected to said input node, a first terminal connected to a predetermined low voltage and a second terminal connected to the gate of said output transistor; and a plurality of P channel transistors each having gates selectively connected to a respective predetermined voltage and each having first and second terminals connected between the second terminal of said first P channel transistor and said N channel transistor.
Claim 3
Dependent Claim
49 words
The output circuitry of claim 1 wherein said plurality of P channel transistors have their first and second terminals connected in parallel and said magnitude control circuitry comprises circuitry to selectively connect said ones of said gates of said plurality of P channel transistors to a predetermined low voltage.
Claim 4
Dependent Claim
39 words
The output circuitry of claim 2 wherein said magnitude control circuitry includes logic circuitry to selectively connect ones of said gates of said plurality of P channel transistors to said predetermined low voltage during operation of the output circuitry.
Claim 5
Dependent Claim
28 words
The output circuitry of claim 3 wherein said logic circuitry is operable to connect ones of said gates of said plurality of P channel transistors responsive to temperature.
Claim 6
Dependent Claim
29 words
The output circuitry of claim 3 wherein said logic circuitry is operable to connect ones of said gates of said plurality of P channel transistors responsive to supply voltage.
Claim 7
Dependent Claim
41 words
The output circuitry of claim 1 wherein said plurality of P channel transistors have their first and second terminals connected in series and said magnitude control circuitry includes bypass circuitry to selectively bypass ones of said plurality of P channel transistors.
Claim 8
Dependent Claim
13 words
The output circuitry of claim 6 wherein said bypass circuitry comprises fusible links.
Claim 9
Dependent Claim
13 words
The output circuitry of claim 6 wherein said bypass circuitry comprises programmable switches.
Claim 10
Dependent Claim
221 words
Output circuitry to reduce inductive voltage spikes in an integrated circuit comprising: an input node for receiving an input voltage signal; an output transistor having first, second and control terminals; voltage control circuitry responsive to the voltage at said input node for controlling the voltage of the control terminal of said output transistor with respect to time, such that the change in output current between the first and second terminals with respect to time has a relatively constant magnitude; and magnitude control circuitry connected to said voltage control circuitry for controlling the magnitude of constant change of output current with respect to time; wherein said output transistor comprises a P channel output transistor and said voltage control circuitry comprises: a P channel transistor having its gate connected to said input node, a first terminal connected to a predetermined high voltage and a second terminal connected to the gate of said output transistor; a first N channel transistor having its gate connected to said input node, a first terminal connected to a predetermined low voltage and a second terminal connected to a first node; and a plurality of N channel transistors each having gates selectively connected to a respective predetermined high voltage and each having first and second terminals connected between the second terminals of said P channel is said N channel.
Claim 11
Dependent Claim
221 words
Output circuitry to reduce inductive voltage spikes in an integrated circuit comprising: an input node for receiving an input voltage signal; an output transistor having first, second and control terminals; voltage control circuitry responsive to the voltage at said input node for controlling the voltage of the control terminal of said output transistor with respect to time, such that the change in output current between the first and second terminals with respect to time has a relatively constant magnitude; and magnitude control circuitry connected to said voltage control circuitry for controlling the magnitude of constant change of output current with respect to time; wherein said output transistor comprises a P channel output transistor and said voltage control circuitry comprises: a P channel transistor having its gate connected to said input node, a first terminal connected to a predetermined high voltage and a second terminal connected to the gate of said output transistor; a first N channel transistor having its gate connected to said input node, a first terminal connected to a predetermined low voltage and a second terminal connected to a first node; and a plurality of N channel transistors each having gates selectively connected to a respective predetermined high voltage and each having first and second terminals connected between the second terminals of said P channel is said N channel.
Claim 12
Dependent Claim
48 words
The output circuitry of claim 9 wherein said plurality of N channel transistors have their first and second terminals connected in parallel and said magnitude control Circuitry comprises circuitry to selectively connect ones of said gates of said plurality of N channels transistors to a predetermined high voltage.
Claim 13
Dependent Claim
38 words
The output circuitry of claim 10 wherein said magnitude control circuitry includes logic circuitry to selectively connect ones of said gates of said plurality of N channel transistors to predetermined high voltage during operation of the output circuitry.
Claim 14
Dependent Claim
33 words
The output circuitry of claim 11 wherein said logic circuitry is operable to connect ones of said gates of said plurality of N channel transistors to said predetermined high voltage responsive to temperature.
Claim 15
Dependent Claim
34 words
The output circuitry of claim 11 wherein said logic circuitry is operable to connect ones of said gates of said plurality of N channel transistors to said predetermined high voltage responsive to supply voltage.
Claim 16
Dependent Claim
41 words
The output circuitry of claim 9 wherein said plurality of N channel transistors have their first and second terminals connected in series and said magnitude control circuitry includes bypass circuitry to selectively bypass ones of said plurality of N channel transistors.
Claim 17
Dependent Claim
13 words
The output circuitry of claim 14 wherein said bypass circuitry comprises fusible links.
Claim 18
Dependent Claim
13 words
The output circuitry of claim 14 wherein said bypass circuitry comprises programmable switches.
References Cited (Backward Citations)
US4518873A
Cited
US4593203A
Cited
US4654548A
Cited
US4700089A
Cited
US4622482A
Cited
US4785203A
Cited
US4760279A
Cited
US4806802A
Cited
US4760292A
Cited
US4818901A
Cited
US4797579A
Cited
US4800298A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-24 | 1994-03-26 | 1994-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-24 | 1998-03-26 | 1998-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-24 | 2002-03-26 | 2002-09-25 | $7700.00 | Window Closed / Lapsed |