CMOS circuit having shoot through current control

Claim 2

A complementary MOS integrated circuit for suppressing a penetration current, comprising: a data input terminal; an output circuit including a first P-channel MOS transistor and a first N-channel MOS transistor connected in series with each other, said output circuit being coupled between first and second power source terminals and an output signal being produced from a common coupling point of said first P-channel and N-channel MOS transistors; and a pre-output circuit connected to drive said output circuit, said pre-output circuit being coupled between said first and second power source terminals and being in parallel with said output circuit, said pre-output circuit including a second P-channel MOS transistor, a second N-channel MOS transistor and a resistance means connected between said second P-channel and N-channel MOS transistors, said second P-channel MOS transistor having its drain terminal connected to the gate terminal of said first P-channel MOS transistor, and said second N-channel MOS transistor having its drain terminal connected to the gate terminal of said first N-channel MOS transistor, said resistance means including a third P-channel MOS transistor and a third N-channel MOS transistor connected in parallel with each other to constitute an analog switch, gate terminals of said third P-channels MOS transistor and said third N-channel MOS transistor each being connected to said data input terminal, and said resistance means being connected between the drain terminals of said second N-channel and P-channel MOS transistors such that the penetration current is suppressed from flowing in said output circuit.

Claim 3

A complementary MOS integrated circuit comprising: a data input terminal; an output circuit including a first P-channel MOS transistor and a first N-channel MOS transistor connected in series with each other, said output circuit being coupled between first and second power source terminals and an output signal being produced from a common coupling point of said first P-channel and N-channel MOS transistors; and a pre-output circuit connected to drive said output circuit, which is coupled between said first and second power source terminals in parallel with said output circuit, said pre-output circuit including a first gate means, a second gate means and a resistance means connected between said first and second gate means, said resistance means comprising first and second analog switches; said second analog switch including a second P-channel MOS transistor whose gate is connected to a first control input terminal and a second N-channel MOS transistor whose gate is connected to a second control input terminal, said second P-channel and N-channel MOS transistors being connected in parallel with each other. said first gate means including a third P-channel MOS transistor whose gate is connected to said data input terminal and a fourth P-channel MOS transistor whose gate is connected to said second control input terminal, said third and fourth P-channel MOS transistor being connected in parallel with each other between said first power source terminal and the gate of said first P-channel MOS transistor of said output circuit; said second gate means including a third N-channel MOS transistor whose gate is connected to said data input terminal and a fourth N-channel MOS transistor whose gate is connected to said first control input terminal to receive a first control signal which is opposite in logic level to a second control signal applied to said second control input terminal, said third and fourth N-channel MOS transistors being connected in parallel with each other between the gate of said first N-channel MOS transistor and said second power source terminal; and said first analog switch including a fifth P-channel MOS transistor whose gate is connected to said data input terminal and a fifth N-channel MOS transistor whose gate is connected to said data input terminal, said fifth P-channel and said fifth N-channel MOS transistors being connected in parallel with each other, said first and second analog switches being series-connected between the gates of said first P-channel and N-channel MOS transistors of said output circuit.

Claim 4

A complementary MOS integrated circuit comprising: a data input terminal; an output circuit including a first P-channel MOS transistor and a first N-channel MOS transistor connected in series with each other, said output circuit being coupled between first and second power source terminals and an output signal being produced from a common coupling point of said first P-channel and N-channel MOS transistors; and a pre-output circuit connected to drive said output circuit, which is coupled between said first and second power source terminals in parallel with said output circuit, said pre-output circuit including a first gate means, a second gate means and a resistance means connected between said first and second gate means, said resistance means comprising first and second analog switches; said second analog switch including a second P-channel MOS transistor whose gate is connected to a first control input terminal and a second N-channel MOS transistor whose gate is connected to a second control input terminal, said second P-channel and N-channel MOS transistors being connected in parallel with each other. said first gate means including a third P-channel MOS transistor whose gate is connected to said data input terminal and a fourth P-channel MOS transistor whose gate is connected to said second control input terminal, said third and fourth P-channel MOS transistor being connected in parallel with each other between said first power source terminal and the gate of said first P-channel MOS transistor of said output circuit; said second gate means including a third N-channel MOS transistor whose gate is connected to said data input terminal and a fourth N-channel MOS transistor whose gate is connected to said first control input terminal to receive a first control signal which is opposite in logic level to a second control signal applied to said second control input terminal, said third and fourth N-channel MOS transistors being connected in parallel with each other between the gate of said first N-channel MOS transistor and said second power source terminal; and said first analog switch including a fifth P-channel MOS transistor whose gate is connected to said data input terminal and a fifth N-channel MOS transistor whose gate is connected to said data input terminal, said fifth P-channel and said fifth N-channel MOS transistors being connected in parallel with each other, said first and second analog switches being series-connected between the gates of said first P-channel and N-channel MOS transistors of said output circuit.

Claim 5

The circuit as defined in claim 2 wherein a series circuit of said first gate means, said first analog switch, said second analog switch and said second gate means is connected between said first and second power source terminals.

Claim 6

The circuit as defined in claim 2 wherein a series circuit of said first gate means, said second analog switch, said first analog switch and said second gate means is connected between sad first and second power source terminals.